Senior Logic Design & Verification Architect

Synopsys Inc; Dublin; On-site; EUR 120,000 - 180,000; Full time

Benefits offered by this job

Health benefits

Total rewards

Job summary

Synopsys Inc. in Ireland is seeking an experienced verification engineer to lead UVM-based ASIC verification efforts for interface IP and silicon validation. You will architect advanced testbenches, write constrained random sequences, and implement assertions for both functional and formal flows.

You will collaborate across teams to ensure coverage goals, mentor junior engineers, and help drive verification standards that scale across projects in a fast‑paced environment.

Qualifications

• 8+ years of hands-on ASIC design verification experience with strong focus on UVM-based functional verification.
• Deep expertise in SystemVerilog, including advanced testbench architecture, constrained random verification, and coverage-driven verification.
• Proven experience implementing SystemVerilog Assertions for functional and formal verification flows.
• Strong programming skills in at least two of: C, SystemVerilog, TCL, Perl, or Python.
• Experience with PCI Express and CXL protocols is a strong plus.

Responsibilities

• Collaborate with design teams to define verification requirements and translate specs into test plans that cover functional, edge case, and performance scenarios.
• Architect and implement UVM testbench environments, including agents, scoreboards, and reusable verification components for interface IP designs.
• Write SystemVerilog test sequences and constrained random stimulus to stress designs and uncover corner cases before silicon.
• Implement SystemVerilog Assertions for simulation-based functional verification and formal verification flows.
• Build and analyze functional and code coverage metrics, identify gaps, and drive coverage closure.
• Lead and mentor a team of verification engineers, teaching UVM methodology, debugging techniques, and testbench architecture best practices.

Skills

UVM

SystemVerilog

Constrained random

Code coverage

Mentoring

Education

Bachelor's or master's in computer/electrical/communication engineering

Tools

Jasper

VC Formal

Cursor

GitHub Copilot

Job description

Synopsys Inc. in Ireland is seeking an experienced verification engineer to lead UVM-based ASIC verification efforts for interface IP and silicon validation. You will architect advanced testbenches, write constrained random sequences, and implement assertions for both functional and formal flows.

You will collaborate across teams to ensure coverage goals, mentor junior engineers, and help drive verification standards that scale across projects in a fast‑paced environment.