Principal ASIC Verification Lead for Interface IP

Synopsys Inc; Dublin; On-site; EUR 90,000 - 130,000; Full time

Job summary

Synopsys Inc in Ireland is seeking an experienced ASIC Digital Verification Engineer to design and implement verification environments and ensure the correctness of Interface IP protocols such as DDR, PCIe, CXL and Ethernet.

You will develop and maintain verification IP and testbenches using SystemVerilog and UVM, mentor junior engineers, and collaborate with design teams to drive coverage and bug fixes, contributing to high-quality silicon products for a range of industries.

Qualifications

• Broad ASIC digital verification experience with Interface IP protocols.
• Strong SystemVerilog and UVM proficiency.
• Familiarity with simulation tools (VCS/ModelSim).
• Ability to mentor junior engineers and communicate with stakeholders.

Responsibilities

• Designing and implementing verification environments for Interface IP protocols.
• Creating and executing detailed test plans for complex ASIC designs.
• Developing and maintaining verification IP and testbenches with SystemVerilog and UVM.
• Collaborating with design and architecture teams to identify and fix bugs.
• Performing functional coverage analysis and driving coverage closure.
• Mentoring and guiding junior verification engineers in best practices.

Skills

ASIC verification

SystemVerilog

UVM methods

DDR protocols

PCIe

Tools

VCS

ModelSim

Job description

Synopsys Inc in Ireland is seeking an experienced ASIC Digital Verification Engineer to design and implement verification environments and ensure the correctness of Interface IP protocols such as DDR, PCIe, CXL and Ethernet.

You will develop and maintain verification IP and testbenches using SystemVerilog and UVM, mentor junior engineers, and collaborate with design teams to drive coverage and bug fixes, contributing to high-quality silicon products for a range of industries.