Senior Verification Engineer, ASIC/FPGA & SystemVerilog

YOH SOLUTIONS LTD; Cambridge; On-site; GBP 70,000 - 100,000; Full time

Job summary

YOH SOLUTIONS LTD is seeking a Senior Verification Engineer to join its engineering team in Cambridge, UK. You will verify complex RTL designs in a collaborative ASIC/FPGA environment, ensuring functional and performance targets are met before production hardware.

You will lead verification planning, develop SystemVerilog/UVM testbenches, and mentor junior engineers while coordinating with design and systems teams across project lifecycles.

Qualifications

• Degree in Electronic Engineering, Computer Engineering or a related discipline.
• Proven experience in verifying ASIC/FPGA designs.
• Strong SystemVerilog and UVM expertise.
• Experience with coverage-driven and assertion-based verification techniques.

Responsibilities

• Develop and execute verification strategies for ASIC/FPGA designs.
• Create and maintain SystemVerilog/UVM testbenches and coverage models.
• Debug RTL and verification issues to ensure quality and performance.
• Collaborate with design, FPGA and systems teams throughout the lifecycle.
• Support automation, regression testing and CI/CD initiatives.
• Mentor junior engineers and participate in technical reviews.

Skills

SystemVerilog

UVM

RTL design

Debugging

Python scripting

Tcl/Bash scripting

Linux

Verification planning

Mentoring

Communication

Education

Bachelor's degree in Electronic Engineering or Computer Engineering

Job description

YOH SOLUTIONS LTD is seeking a Senior Verification Engineer to join its engineering team in Cambridge, UK. You will verify complex RTL designs in a collaborative ASIC/FPGA environment, ensuring functional and performance targets are met before production hardware.

You will lead verification planning, develop SystemVerilog/UVM testbenches, and mentor junior engineers while coordinating with design and systems teams across project lifecycles.