Senior Verification Engineer

Spectrum IT Recruitment; Southampton; On-site; GBP 70,000 - 90,000; Full time

Job summary

Spectrum IT Recruitment is seeking a Senior Verification Engineer to join a specialist RTL team in the Southampton area. You will own UVM verification of complex wireless IP and modem subsystems, ensuring designs meet functional, performance and quality requirements ahead of FPGA deployment and ASIC tape-out.

The role involves developing verification plans, building SV/UVM test environments, and mentoring junior engineers while contributing to CI workflows and integration effort across multiple

Qualifications

• Degree in Electronic Engineering or a related discipline.
• At least 3 years' experience verifying digital ASIC and/or FPGA designs.
• Strong SystemVerilog and UVM experience.
• Good understanding of RTL design principles and hardware implementation.
• Experience with coverage-driven and assertion-based verification.
• Linux proficiency with Python, Tcl or Bash scripting.
• Strong analytical, debugging and problem-solving skills.
• Experience using AI to accelerate verification while maintaining quality.
• Ability to collaborate effectively across multiple engineering teams.

Responsibilities

• Develop verification plans from design and architecture specifications.
• Create and maintain SystemVerilog/UVM verification environments.
• Develop testbenches, assertions, scoreboards and coverage models.
• Carry out directed and constrained-random verification.
• Analyse coverage and debug RTL and verification issues.
• Support subsystem and system-level integration.
• Contribute to automation, regression testing and CI workflows.
• Participate in design reviews and verification sign-off.
• Mentor and support junior engineers.

Skills

Electronic Engineering degree

3+ years verification experience

SystemVerilog & UVM

RTL design principles

Coverage-driven verification

Linux scripting (Python/Tcl/Bash)

Analytical & debugging

AI-assisted verification

Cross-team collaboration

Education

Bachelor's degree in Electronics/Computer Engineering

Tools

SystemVerilog

UVM

Job description

We're looking for a Senior Verification Engineer to join a specialist RTL team developing advanced communications technology across ASIC and FPGA platforms. You'll take responsibility for the UVM verification of complex wireless communications IP and modem subsystems, ensuring designs meet functional, performance, and quality requirements ahead of FPGA deployment and ASIC tape-out. This is an opportunity to work on technically challenging projects covering IP development, integration, and verification, while also supporting and mentoring more junior engineers.

Skills Required

• Degree in Electronic Engineering, Computer Engineering, or a related discipline.
• At least 3 years' experience verifying digital ASIC and/or FPGA designs.
• Strong SystemVerilog and UVM experience.
• Good understanding of RTL design principles and hardware implementation.
• Experience with coverage-driven and assertion-based verification.
• Linux proficiency with Python, Tcl or Bash scripting skills.
• Strong analytical, debugging and problem-solving skills.
• Experience using AI to accelerate verification while maintaining quality.
• Ability to collaborate effectively across multiple engineering teams.

What You'll Be Doing

• Develop verification plans from design and architecture specifications.
• Create and maintain SystemVerilog/UVM verification environments.
• Develop testbenches, assertions, scoreboards and coverage models.
• Carry out directed and constrained-random verification.
• Analyse coverage and debug RTL and verification issues.
• Support subsystem and system-level integration.
• Contribute to automation, regression testing and CI workflows.
• Participate in design reviews and verification sign-off.
• Mentor and support junior engineers.

Desirable Experience

• 4G/5G, NTN, satellite communications or DSP systems.
• Modem architectures and Layer 1 processing.
• Formal Verification, FPGA prototyping and CI environments.
• MATLAB or equivalent modelling tools.