Senior ASIC Design & Verification Architect

Synopsys, Inc.; United Kingdom; On-site; GBP 70,000 - 90,000; Full time

Job summary

Synopsys, Inc. in the United Kingdom is seeking an enthusiastic ASIC Digital Design Engineer focused on verification and Interface IP. You will translate high-level requirements into robust digital designs and verification environments.

Collaborate with design and architecture teams to identify bugs, develop testbenches with SystemVerilog/UVM, drive coverage closure, mentor junior engineers, and document specs and verification reports.

Qualifications

• Experience with SystemVerilog/UVM for complex IP verification.
• Strong understanding of digital design and verification methodologies.
• Proficiency in creating and maintaining verification environments.

Responsibilities

• Designing and implementing verification environments for Interface IP protocols.
• Collaborating with design and architecture teams to identify bugs.
• Performing all task related to verifying a complex digital IP including detailed test plans, functional coverage analysis and driving coverage closure.
• Mentoring and guiding junior verification engineers in best practices and methodologies.
• Conducting design and verification reviews and providing constructive feedback to improve overall quality and functionality.
• Documenting design specifications, test plans, and verification reports.

Skills

SystemVerilog

UVM

SVA

Digital design

Verification methodologies

Python scripting

Perl scripting

Testbench development

Job description

Synopsys, Inc. in the United Kingdom is seeking an enthusiastic ASIC Digital Design Engineer focused on verification and Interface IP. You will translate high-level requirements into robust digital designs and verification environments.

Collaborate with design and architecture teams to identify bugs, develop testbenches with SystemVerilog/UVM, drive coverage closure, mentor junior engineers, and document specs and verification reports.