Senior Verification Engineer – RTL/UVM, Hybrid Work

AccelerComm Ltd; West of England; Ibrido; GBP 60.000 - 90.000; Tempo pieno

Vantaggi offerti da questo lavoro

Bonus up to 20%

EMI share options

Pension

Private health insurance

Hybrid working

Flexible working hours

Descrizione del lavoro

AccelerComm Ltd. is seeking a Senior Verification Engineer in Bristol, UK to lead RTL verification across ASIC/FPGA designs. You will develop verification plans, build SystemVerilog/UVM environments, and drive robust validation prior to deployment. Hybrid working is available.

The role requires 3+ years in digital verification, strong SystemVerilog/UVM skills, Linux scripting, and a collaborative mindset to work across multiple teams.

Competenze

• Degree in Electronic or Computer Engineering or related discipline.
• 3+ years experience verifying digital ASIC and/or FPGA designs.
• Strong SystemVerilog and UVM skills.
• Linux proficiency and scripting skills (Python, Tcl or Bash).
• Strong analytical, debugging and problem-solving skills.
• Experience using AI to accelerate verification without sacrificing quality.
• Ability to work across multiple teams.

Mansioni

• Develop verification plans from design and architecture specifications.
• Create and maintain SystemVerilog/UVM verification environments.
• Develop testbenches, assertions, scoreboards and coverage models.
• Execute directed and constrained-random verification.
• Analyse coverage and debug RTL and verification issues.
• Support subsystem and system-level integration activities.
• Contribute to automation, regression and CI workflows.
• Participate in design reviews and verification sign-off.
• Mentor and support junior colleagues.

Conoscenze

SystemVerilog

UVM

Scripting (Python/Tcl/Bash)

Linux

Debugging

AI in verification

Team collaboration

ASIC/FPGA verification

Formazione

Degree in Electronic / Computer Engineering or related discipline

Descrizione del lavoro

AccelerComm Ltd. is seeking a Senior Verification Engineer in Bristol, UK to lead RTL verification across ASIC/FPGA designs. You will develop verification plans, build SystemVerilog/UVM environments, and drive robust validation prior to deployment. Hybrid working is available.

The role requires 3+ years in digital verification, strong SystemVerilog/UVM skills, Linux scripting, and a collaborative mindset to work across multiple teams.