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AccelerComm Ltd. is seeking a Senior Verification Engineer in Bristol, UK to lead RTL verification across ASIC/FPGA designs. You will develop verification plans, build SystemVerilog/UVM environments, and drive robust validation prior to deployment. Hybrid working is available.
The role requires 3+ years in digital verification, strong SystemVerilog/UVM skills, Linux scripting, and a collaborative mindset to work across multiple teams.
Department: Hardware
Employment Type: Full Time
Location: Bristol, UK
Our RTL team delivers efficient ASIC and FPGA implementations of advanced communications algorithms, working across IP development, integration and verification. To support this work, we are looking for a Senior Verification Engineer to support the complete UVM verification of Accelercomm IP.
Responsible for verification of RTL implementations for advanced wireless communications IP and modem subsystems, ensuring designs meet functional, performance and quality requirements prior to FPGA deployment and ASIC tape-out.
We pay competitive salaries which depend on skills and experience.
We offer a bonus scheme which pays up to 20% of salary annually, depending on performance. This is in addition to EMI share options, issued periodically.
We offer a range of good quality company benefits including pension and private health insurance.
We operate flexible working hours and offer hybrid working.