Senior CPU Verification Architect

QualityAI; Greater London; On-site; GBP 90,000 - 120,000; Full time

Job summary

QualityAI is seeking a senior hardware verification engineer in the United Kingdom to join a Research and Development team. You will build verification components and drive verification closure for digital designs, contributing to high-performance hardware platforms loved by customers worldwide.

You will create constrained-random verification environments using SystemVerilog and UVM, and perform formal verification with SVA and leading formal tools.

Qualifications

• Bachelors degree in electrical engineering or equivalent practical experience.
• 8 years of verification experience using standard verification methodologies.
• Experience verifying digital RTL at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.

Responsibilities

• Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
• Create and enhance constrained-random verification environments using SystemVerilog and UVM or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
• Identify and write all types of coverage measures for corner-cases.
• Debug tests with design engineers to deliver functionally correct design blocks.
• Close coverage measures to identify verification holes and to show progress towards tape-out.

Education

Bachelors degree in electrical engineering

Masters degree

Tools

SystemVerilog

UVM

SVA

Specman/E

Formal tools

Job description

QualityAI is seeking a senior hardware verification engineer in the United Kingdom to join a Research and Development team. You will build verification components and drive verification closure for digital designs, contributing to high-performance hardware platforms loved by customers worldwide.

You will create constrained-random verification environments using SystemVerilog and UVM, and perform formal verification with SVA and leading formal tools.