Senior Design Verification Engineer – Mixed-Signal ASICs

IC Resources; City of Edinburgh; Hybrid; GBP 60,000 - 90,000; Full time

Benefits offered by this job

Competitive base salary

RSUs and annual bonus

Flexible work options

Job summary

A leading semiconductor company in Edinburgh seeks a Senior Design Verification Engineer to ensure the correctness of complex digital and mixed-signal ASIC designs. The role involves developing verification plans, mentoring engineers, and collaborating with design teams. Candidates should have over 5 years of experience, strong SystemVerilog and UVM skills, and familiarity with ASIC development flows. The position offers competitive salary, RSUs, and flexible work options for UK-based engineers.

Qualifications

• 5+ years’ experience in digital and/or mixed-signal design verification.
• Strong proficiency in SystemVerilog, UVM, and leading simulation tools.
• Solid understanding of RTL design and ASIC development flows.

Responsibilities

• Develop and execute comprehensive verification plans for complex mixed-signal ASIC designs.
• Mentor junior engineers and drive improvements in verification methodologies.
• Collaborate closely with design engineers to interpret specifications.

Skills

SystemVerilog

UVM

Digital design principles

Problem-solving skills

Tools

Synopsys VCS

Cadence Xcelium

Python

Perl

Shell

Job description

A leading semiconductor company in Edinburgh seeks a Senior Design Verification Engineer to ensure the correctness of complex digital and mixed-signal ASIC designs. The role involves developing verification plans, mentoring engineers, and collaborating with design teams. Candidates should have over 5 years of experience, strong SystemVerilog and UVM skills, and familiarity with ASIC development flows. The position offers competitive salary, RSUs, and flexible work options for UK-based engineers.