Senior Verification Engineer

YOH SOLUTIONS LTD; Cambridge; On-site; GBP 70,000 - 100,000; Full time

Job summary

YOH SOLUTIONS LTD is seeking a Senior Verification Engineer to join its engineering team in Cambridge, UK. You will verify complex RTL designs in a collaborative ASIC/FPGA environment, ensuring functional and performance targets are met before production hardware.

You will lead verification planning, develop SystemVerilog/UVM testbenches, and mentor junior engineers while coordinating with design and systems teams across project lifecycles.

Qualifications

• Degree in Electronic Engineering, Computer Engineering or a related discipline.
• Proven experience in verifying ASIC/FPGA designs.
• Strong SystemVerilog and UVM expertise.
• Experience with coverage-driven and assertion-based verification techniques.

Responsibilities

• Develop and execute verification strategies for ASIC/FPGA designs.
• Create and maintain SystemVerilog/UVM testbenches and coverage models.
• Debug RTL and verification issues to ensure quality and performance.
• Collaborate with design, FPGA and systems teams throughout the lifecycle.
• Support automation, regression testing and CI/CD initiatives.
• Mentor junior engineers and participate in technical reviews.

Skills

SystemVerilog

UVM

RTL design

Debugging

Python scripting

Tcl/Bash scripting

Linux

Verification planning

Mentoring

Communication

Education

Bachelor's degree in Electronic Engineering or Computer Engineering

Job description

An innovative technology company developing advanced digital hardware and signal processing solutions is seeking a Senior Verification Engineer to join its growing engineering team in either

Working within a collaborative ASIC and FPGA development environment, you will play a key role in verifying complex RTL designs, ensuring products meet functional, quality and performance requirements before deployment into production hardware.

This is an excellent opportunity to work on technically challenging projects alongside experienced hardware, FPGA and verification engineers.

The Role

As a Senior Verification Engineer, you will be responsible for planning, developing and executing verification activities for complex digital designs and subsystems.

You will work closely with design engineers throughout the development lifecycle, helping to ensure robust verification methodologies, high-quality deliverables and successful project outcomes.

Key Responsibilities

• Develop and execute verification strategies for complex ASIC and FPGA designs.
• Create and maintain SystemVerilog/UVM verification environments, testbenches and coverage models.
• Debug RTL and verification issues, ensuring designs meet quality and performance requirements.
• Collaborate with design, FPGA and systems teams throughout the development lifecycle.
• Support automation, regression testing and continuous improvement initiatives.
• Mentor junior engineers and contribute to technical reviews.
• Degree in Electronic Engineering, Computer Engineering or a related discipline.
• Proven experience verifying ASIC and/or FPGA designs.
• Strong SystemVerilog and UVM expertise.
• Good understanding of RTL design and digital hardware development.
• Experience with coverage-driven and assertion-based verification techniques.
• Linux proficiency and scripting skills (Python, Tcl, Bash or similar).
• Strong debugging, analytical and communication skills.
• Communications, networking, aerospace, defence or other high-performance digital systems.
• Digital signal processing (DSP) or complex hardware architectures.
• Formal Verification or FPGA prototyping.
• CI/CD, automated regression environments or MATLAB/Simulink.