Senior IC Layout Engineer — Hybrid, High-Speed SerDes

IC Resources; Cambridge; Hybrid; GBP 70,000 - 95,000; Full time

Benefits offered by this job

Pension

Private medical

Visa sponsorship

Relocation assistance

Job summary

IC Resources in Cambridge is seeking a Senior IC Layout Engineer to own custom analog layout and verification of circuits, cells, blocks, and IP for high-speed SerDes and memory IO in advanced semiconductor technology nodes. Hybrid working is available with 3 days a week in the office.

The ideal candidate will have a strong background in analog IC layout, particularly on high-speed designs, with proficiency in Cadence Virtuoso, Spectre/HSpice, Calibre/PVS, and parasitics extraction.

Qualifications

• Experience in analog IC layout and verification.
• Strong background in high-speed designs preferred.

Responsibilities

• Custom analog layout of circuits and blocks for high-speed serdes or memory IO.
• Layout of high-speed and high-frequency circuits including amplifiers and PLLs.
• Apply layout techniques for parasitic minimisation, matching, power grids and ESD.

Job description

IC Resources in Cambridge is seeking a Senior IC Layout Engineer to own custom analog layout and verification of circuits, cells, blocks, and IP for high-speed SerDes and memory IO in advanced semiconductor technology nodes. Hybrid working is available with 3 days a week in the office.

The ideal candidate will have a strong background in analog IC layout, particularly on high-speed designs, with proficiency in Cadence Virtuoso, Spectre/HSpice, Calibre/PVS, and parasitics extraction.