Senior IC Layout Engineer

IC Resources; Cambridge; Híbrido; GBP 70.000 - 95.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Pension

Private medical

Visa sponsorship

Relocation assistance

Descripción de la vacante

IC Resources in Cambridge is seeking a Senior IC Layout Engineer to own custom analog layout and verification of circuits, cells, blocks, and IP for high-speed SerDes and memory IO in advanced semiconductor technology nodes. Hybrid working is available with 3 days a week in the office.

The ideal candidate will have a strong background in analog IC layout, particularly on high-speed designs, with proficiency in Cadence Virtuoso, Spectre/HSpice, Calibre/PVS, and parasitics extraction.

Formación

• Experience in analog IC layout and verification.
• Strong background in high-speed designs preferred.

Responsabilidades

• Custom analog layout of circuits and blocks for high-speed serdes or memory IO.
• Layout of high-speed and high-frequency circuits including amplifiers and PLLs.
• Apply layout techniques for parasitic minimisation, matching, power grids and ESD.

Descripción del empleo

This is a new opportunity for a Senior IC Layout Engineer to join our rapidly scaling Semiconductor client based in Cambridge. Hybrid working is available with this role, 3 days a week in the office.

As the Senior IC Layout Engineer, you will own the custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed SerDes up to and beyond 28Gb/s and/or memory IO in advanced semiconductor technology nodes. You will have the opportunity to lead chip layout activities; hence there's a lot of scope for career progression and satisfaction as you see your work in the final product.

As the ideal candidate you will be an experienced Analog IC Layout Engineer, ideally a background working on high speed designs, although high-speed is not essential.

• Custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or high frequency circuits
• Layout of high-speed or high frequency circuits such as amplifiers, oscillators, phase-locked loops, delay-locked loops, biasing, buffers, regulators, filters, data converters
• Layout approaches and techniques for high-speed circuits, matching constraints, minimisation of parasitics, power grids and ESD requirements
• Modern semiconductor process technologies including 28nm, 14/16nm, 7nm
• EDA tools for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc

On offer is a competitive salary, benefits package (including pension, private medical), visa sponsorship and relocation assistance where required.