Lead Analog Layout Engineer for High-Speed AI Interconnects

Kandou AI

Reading

On-site

GBP 83,000 - 129,000

Full time

14 days+

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Job summary

Kandou is seeking an Analog Layout Engineer (Lead) to drive custom analog layout and verification for high-speed SerDes and memory interfaces across 28nm to 7nm nodes. You will collaborate with design teams to implement robust layouts, ensure IP and chip integration, and engage with customers on requirements and IP delivery.

The role demands hands-on experience in analog layout and strong communication skills in a fast-paced semiconductor environment. EU/CH/UK location flexibility is offered.

Qualifications

  • Custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or HF/RF circuits.
  • Layout of high-speed analog circuits (amplifiers, oscillators, phase-locked loops, delay-locked loops).
  • Understanding of layout approaches and techniques for high-speed circuits, matching constraints and parasitics minimization.

Responsibilities

  • Position in custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed chip to chip communication links.
  • Layout and verification of very high-speed analog circuits.
  • Interact closely with the design team to understand requirements and implement solutions.
  • Support IP and chip level integration.
  • Support and interact with customers on requirements, and IP delivery.

Skills

Strong ownership
Good communicator
Team player

Education

Graduate in E.E.

Tools

Cadence Virtuoso
Spectre/HSpice
Calibre/PVS DRC/LVS

Job description

Kandou is seeking an Analog Layout Engineer (Lead) to drive custom analog layout and verification for high-speed SerDes and memory interfaces across 28nm to 7nm nodes. You will collaborate with design teams to implement robust layouts, ensure IP and chip integration, and engage with customers on requirements and IP delivery.

The role demands hands-on experience in analog layout and strong communication skills in a fast-paced semiconductor environment. EU/CH/UK location flexibility is offered.

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