Lead Analog Layout Engineer – High-Speed SerDes Expert

Kandou Bus SA; United Kingdom; Remote; GBP 90,000 - 130,000; Full time

Job summary

Kandou is seeking an Analog Layout Engineer (Lead) to drive layout and verification of high-speed analog circuits and IP for multi-Gigabit data links across advanced nodes (28nm, 14/16nm, 7nm). You will interact with design teams, support IP integration, and assist customers on requirements and IP delivery, including exposure to flip-chip packaging.

Location flexibility across EU/CH/UK. Must have proven experience in custom analog layout for high-speed links, and strong knowledge of layout

Qualifications

• Self-motivated with strong sense of ownership and responsibility.
• Good communicator and team player.
• Background in Semiconductor Physics.

Responsibilities

• Position in custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed chip to chip communication links (SerDes up to and beyond 28Gb/s and/or memory IO) in advanced semiconductor technology nodes
• Layout and verification of very high-speed analog circuits
• Interact closely with the design team to understand requirements and implement solutions
• Support IP and chip level integration
• Support and interact with customers on requirements, and IP delivery
• Exposure to flip-chip package technologies

Skills

Self-motivation

Communication

Team player

Education

Graduate in E.E.

Job description

Kandou is seeking an Analog Layout Engineer (Lead) to drive layout and verification of high-speed analog circuits and IP for multi-Gigabit data links across advanced nodes (28nm, 14/16nm, 7nm). You will interact with design teams, support IP integration, and assist customers on requirements and IP delivery, including exposure to flip-chip packaging.

Location flexibility across EU/CH/UK. Must have proven experience in custom analog layout for high-speed links, and strong knowledge of layout