Senior IC Layout Engineer – Cambridge

IC Resources; Cambridgeshire and Peterborough; Hybrid; GBP 70,000 - 100,000; Full time

Benefits offered by this job

Pension

Private medical

Visa sponsorship

Relocation assistance

Job summary

IC Resources is seeking a Senior IC Layout Engineer for our Cambridge-based semiconductor client. The role offers hybrid working with three days in the office weekly.

You will own custom analog layout and verification for multi-Gigabit SerDes and memory IO in advanced nodes, leading layout activities and driving career progression as your work appears in final products.

Qualifications

• Experience in analog IC layout for multi-Gigabit SerDes or memory IO.
• Background in high-speed or RF/high-frequency circuits is a plus.
• Familiar with layout techniques to minimise parasitics and ensure power integrity.

Responsibilities

• Own the custom analog layout and verification of circuits, blocks and IP; lead chip layout activities.
• Collaborate with design teams to deliver layouts for advanced process nodes and ensure design-for-manufacturing compliance.

Skills

Analog IC Layout

High-speed design

IP/Block layout

Layout verification

Chips/SerDes

Tools

Cadence Virtuoso

Spectre/HSpice

Calibre/PVS

Parasitics modelling

Job description

This is a new opportunity for a Senior IC Layout Engineer to join our rapidly scaling Semiconductor client based in Cambridge. Hybrid working is available with this role, 3 days a week in the office.

As the Senior IC Layout Engineer, you will own the custom layout and verification of analog circuits, cells, blocks, and IP for multi-Gigabit high speed SerDes up to and beyond 28Gb/s and/or memory IO in advanced semiconductor technology nodes. You will have the opportunity to lead chip layout activities; hence there’s a lot of scope for career progression and satisfaction as you see your work in the final product.

As the ideal candidate you will be an experienced Analog IC Layout Engineer, ideally a background working on high speed designs, although high-speed is not essential.

Experience is required in some or all of the following;

• Custom analog layout of circuits and blocks for multi-Gigabit serial data-link transceivers or high frequency circuits
• Layout of high-speed or high frequency circuits such as ,amplifiers, oscillators, phase-locked loops, delay-locked loops, biasing, buffers, regulators, filters, data converters
• Layout approaches and techniques for high-speed circuits, matching constraints, minimisation of parasitics, power grids and ESD requirements
• Modern semiconductor process technologies including 28nm, 14/16nm, 7nm
• EDA tools for design and verification like Cadence Virtuoso, Spectre/HSpice, Calibre/PVS DRC/LVS, parasitics extraction and modelling, EM, and IR drop, ESD, etc

On offer is a competitive salary, benefits package (including pension, private medical), visa sponsorship and relocation assistance where required.