Senior IC Layout Engineer — Hybrid & RSU Package

IC Resources; Oxford; Híbrido; GBP 90.000 - 120.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

RSU package

Hybrid working

Descripción de la vacante

IC Resources is seeking a Senior IC Layout Engineer in Oxford. The role involves taking chip designs from requirements through physical implementation and tape-out in a hybrid work setting.

Ideal candidates have hands-on IC layout experience, multi-layer design skills, and familiarity with Cadence tools and manufacturing constraints. You will collaborate with design, engineering and fabrication partners to deliver complex chip projects.

Formación

• Experience with complex, multi-layer IC or semiconductor layout.
• Ability to translate requirements into physical designs and understand chip interactions.
• Experience taking designs through to tape-out.

Responsabilidades

• Take ownership of chip designs through the full development process from requirements to tape-out.
• Translate system and design requirements into practical chip-level physical implementations.
• Design and lay out complex, multi-layer devices with detailed metal routing and interconnects.
• Consider interfaces and compatibility between technologies and components within the design.
• Collaborate with scientists, engineers and fabrication teams to understand requirements and resolve constraints.
• Work with multiple teams to ensure designs are feasible and aligned with manufacturing requirements.
• Identify and resolve layout and physical-design challenges throughout development.
• Take responsibility for projects and drive them through to tape-out.
• Contribute to improving layout methodologies, processes and automation within the design team.

Conocimientos

IC layout

Cadence tools

Tape-out

Metal routing

Physical design

Design rules

Collaboration

Project ownership

Herramientas

Cadence

Descripción del empleo

IC Resources is seeking a Senior IC Layout Engineer in Oxford. The role involves taking chip designs from requirements through physical implementation and tape-out in a hybrid work setting.

Ideal candidates have hands-on IC layout experience, multi-layer design skills, and familiarity with Cadence tools and manufacturing constraints. You will collaborate with design, engineering and fabrication partners to deliver complex chip projects.