SoC Design Engineer: PCIe/DDR RTL Expert – Hybrid

Arm Limited; Sheffield; Hybrid; GBP 60,000 - 100,000; Full time

Job summary

Arm Limited in the United Kingdom seeks a creative SoC Design Engineer to contribute to specification, RTL development and verification of advanced SoCs. You will join a team across Manchester and Cambridge, collaborating with multiple groups to design Arm-based products and drive next-generation compute on Arm devices.

You will integrate subsystems such as PCIe, DDR/LPDDR, HBM and Ethernet, author micro-architecture specs and support backend timing closure, while advancing design methodologies

Qualifications

• Experience crafting subsystems for PCIe, DDR/LPDDR, HBM, UCIe and Ethernet.
• RTL design using Verilog and SystemVerilog.
• Satisfactory static checks (Lint/CDC/RDC), synthesis and timing analysis.
• Exposure to all design stages from concept to verification and documentation.
• Ability to produce specifications and design documentation.
• Shell scripting knowledge (Tcl, Perl, Python).

Responsibilities

• Integrate complex IP like CPU Cluster, PCIe, DDR, and other High-Speed IO IP for SoCs.
• Write micro-architecture specs, develop RTL, fix bugs, and run design checks.
• Work with verification to analyse test plans and debug design issues.
• Support backend implementation by aiding floor planning, constraints, and timing closure.
• Contribute to enhancing design methodologies and quality standards.
• Guide and support team members to ensure project success.
• Assist Project Management with activities, plans, and schedules.

Skills

PCIe

DDR/LPDDR

HBM

UCIe

Ethernet

RTL Design

Static checks

Synthesis

Timing Analysis

Power Management

Clock Domain Crossing

Design Lifecycle

Documentation

Scripting

Tools

Arm familiarity

C/C++ (high level)

Embedded OS concepts

Job description

Arm Limited in the United Kingdom seeks a creative SoC Design Engineer to contribute to specification, RTL development and verification of advanced SoCs. You will join a team across Manchester and Cambridge, collaborating with multiple groups to design Arm-based products and drive next-generation compute on Arm devices.

You will integrate subsystems such as PCIe, DDR/LPDDR, HBM and Ethernet, author micro-architecture specs and support backend timing closure, while advancing design methodologies