Lead PCIe/CXL Verification Engineer (Hybrid)

CamWebDir; United Kingdom; Hybrid; GBP 80,000 - 120,000; Full time

Job summary

Arm’s Solutions Engineering team seeks experienced PCIe and CXL verification experts to validate high-speed IOs at sub-system level. Join engineers across UK/US/Canada/India to build next-gen SoCs using 3nm nodes and advanced 3D packaging, delivering industry-leading performance.

You will craft test plans, develop SystemVerilog/Verilog/UVM testbenches, verify IO virtualization with SMMU, and collaborate with RTL, architecture and other IP teams to ensure robust PCIe/CXL integration.

Qualifications

• Bachelor's or Master's in CS or EE or related field.
• 5+ years in verification of PCIe/CXL subsystems or SoCs.
• Strong Verilog HDL knowledge.
• Experience with SystemVerilog, UVM and formal methods.
• Experience with PCIe & CXL IPs and emulation-friendly transactors.

Responsibilities

• Craft test plans and develop SystemVerilog/Verilog/UVM testbenches.
• Verify IO virtualization with Arm SMMU and PCIe/CXL sub-systems.
• Debug test failures and improve verification methodologies.
• Collaborate with RTL, architecture and other IP teams.
• Guide junior engineers and balance project activities.

Skills

Subsystem verification

PCIe verification

CXL verification

UVM verification

Verilog HDL

SystemVerilog

Test plan development

Emulation

Python/Perl scripting

Interoperability testing

Education

Bachelor's or Master’s degree in Computer Science or Electrical/Computer Engineering

Tools

Emulation platforms

UVM testbenches

SMMU integration

Job description

Arm’s Solutions Engineering team seeks experienced PCIe and CXL verification experts to validate high-speed IOs at sub-system level. Join engineers across UK/US/Canada/India to build next-gen SoCs using 3nm nodes and advanced 3D packaging, delivering industry-leading performance.

You will craft test plans, develop SystemVerilog/Verilog/UVM testbenches, verify IO virtualization with SMMU, and collaborate with RTL, architecture and other IP teams to ensure robust PCIe/CXL integration.