Principal Interconnect IP Design Engineer (RISC‑V/TileLink)

SiFive; Cambridge; On-site; GBP 172,668 - 211,039; Full time

Job summary

SiFive is seeking a principal‑level hardware engineer to design industry‑leading CPU and interconnect IP, driving RISC‑V adoption across SOC designs. You will build highly configurable hardware generators using Chisel/Scala and integrate them into SiFive’s Chisel/FIRRTL workflow.

The role emphasizes scalable IP design, fast time‑to‑market, and collaboration across verification and design teams to deliver high‑quality, performant solutions.

Qualifications

• Extensive experience with RISC-V architectures and interconnect IP.
• Experience designing hardware as configurable software generators.
• Strong verification planning and creation of testbenches.

Responsibilities

• Architect and implement TileLink interconnect and related RTL generators in Chisel.
• Extend configurability of hardware designs for various connections.
• Collaborate with verification to create verification plans and test suites.
• Document designs and maintain a knowledge base for immediate reuse.
• Integrate new content into Chisel/FIRRTL framework and improve auto‑configuration.

Skills

RISC-V knowledge

RTL design

Chisel/Scala

NoC interconnect

Bus protocols

Verilog/SystemVerilog

Compiler infra

Unit testing

Documentation

Team player

Education

BS/MS in EE/CE/CS

Tools

Git/GitHub

Jira

Confluence

Job description

SiFive is seeking a principal‑level hardware engineer to design industry‑leading CPU and interconnect IP, driving RISC‑V adoption across SOC designs. You will build highly configurable hardware generators using Chisel/Scala and integrate them into SiFive’s Chisel/FIRRTL workflow.

The role emphasizes scalable IP design, fast time‑to‑market, and collaboration across verification and design teams to deliver high‑quality, performant solutions.