PPA Architect for High-Performance AI Chips

Fractile; Greater London; On-site; GBP 90,000 - 140,000; Full time

Benefits offered by this job

Private Medical

Dental and Vision Insurance

Contributory Pension

25 Days holiday + bank holidays

Life/Critical Illness Insurance

Job summary

Fractile, a UK-based company, seeks an experienced hardware professional to optimize datapath RTL and drive PPA improvements for frontier AI accelerators. You will work across the hardware stack to deliver high-performance, power-efficient compute silicon in a fast-paced environment.

You will collaborate with PD, EDA, and software teams to translate performance targets into concrete RTL decisions, manage timing closure, and contribute to next-generation AI hardware architectures.

Qualifications

• Strong datapath background with emphasis on PPA, timing and power.
• Experience driving datapath PPC/RTL changes end-to-end and validating impact.
• Knowledge of fixed-point, floating-point, and quantized arithmetic design.
• Deep understanding of PPA trade-offs and translating targets into RTL decisions.
• Experience with low-power design techniques and timing-aware RTL.
• Familiarity with synthesis tools and IP libraries; track record of PPA improvements.
• Experience with formal verification or equivalence checking.
• Ability to collaborate with PD engineers to close timing on critical paths.

Responsibilities

• Own datapath RTL design and optimization for high-performance compute silicon.
• Analyze bottlenecks, propose RTL changes, and measure impact against targets.
• Collaborate with software, silicon and modelling teams to accelerate hardware delivery.
• Iterate on timing, power, and area trade-offs across the design cycle.

Skills

Datapath optimization

Pipelining and retiming

RTL timing closure

Low-power design techniques

Formal verification

PD collaboration for PPA

Education

Bachelor's or higher in EE/CS

Tools

Synopsys Design Compiler/Fusion Compiler

Cadence Genus

DesignWare IP

Job description

Fractile, a UK-based company, seeks an experienced hardware professional to optimize datapath RTL and drive PPA improvements for frontier AI accelerators. You will work across the hardware stack to deliver high-performance, power-efficient compute silicon in a fast-paced environment.

You will collaborate with PD, EDA, and software teams to translate performance targets into concrete RTL decisions, manage timing closure, and contribute to next-generation AI hardware architectures.