Senior DFT Architect for AI Accelerator SoC

Fractile; Greater London; On-site; GBP 110,000 - 150,000; Full time

Benefits offered by this job

Private Medical

Equity & Ownership

25 Days holiday

Life/Critical Illness Insurance

Job summary

Fractile is hiring a Senior/Principal DFT Engineer in the United Kingdom to own and advance the DFT architecture for a high-performance AI accelerator SoC. You will drive strategy, signoff criteria, and seamless tool integration across RTL and physical design to enable robust, scalable test at scale.

The role requires 8+ years of DFT experience, ownership of a large tapeout, and deep expertise in scan, compression, ATPG, and MBIST, with proficiency in Synopsys or Tessent toolchains.

Qualifications

• 8+ years of experience in DFT for ASIC/SoC designs.
• Ownership of DFT architecture on at least one large tapeout.
• Deep expertise in scan, compression, ATPG, and MBIST.
• Experience with industry tools such as Synopsys or Tessent.

Responsibilities

• Own and define the DFT architecture for a large AI accelerator SoC (scan, compression, MBIST, LBIST, boundary scan).
• Set DFT strategy, methodology, flow and signoff criteria.
• Drive integration of DFT tools and flows into the overall EDA environment.
• Define hierarchical DFT approach for multi-core designs and large memory systems.
• Define scan architecture, compression strategy, and ATPG approach.
• Define memory test and repair strategy for large embedded RAM.
• Establish power-aware and at-speed test strategies.
• Work closely with RTL and physical design to ensure clean DFT integration and timing closure.
• Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test and yield ramp.
• Mentor and guide DFT engineers

Skills

DFT architecture

ASIC/SoC design

ATPG/MBIST

Clocking/resets/power domains

Silicon bring-up/debug

Synopsys/Tessent tools

Tools

Synopsys/Tessent

Job description

Fractile is hiring a Senior/Principal DFT Engineer in the United Kingdom to own and advance the DFT architecture for a high-performance AI accelerator SoC. You will drive strategy, signoff criteria, and seamless tool integration across RTL and physical design to enable robust, scalable test at scale.

The role requires 8+ years of DFT experience, ownership of a large tapeout, and deep expertise in scan, compression, ATPG, and MBIST, with proficiency in Synopsys or Tessent toolchains.