Senior/Principal Physical Design Engineer

Fractile; Greater London; On-site; GBP 70,000 - 90,000; Full time

Job summary

A pioneering AI technology firm in Greater London is seeking a highly skilled Senior/Principal Physical Design Engineer to lead the physical implementation of next‑generation chip designs. This role involves driving complex IC designs from synthesis to sign‑off, collaborating with cross‑functional teams to optimise performance, power, and area. Candidates should have a strong background in EDA tools and advanced technology nodes, alongside excellent problem-solving abilities and teamwork skills.

Qualifications

• 7+ years of experience in physical design for advanced technology nodes.
• Strong proficiency in EDA tools for place & route, STA, and sign‑off.
• Experience with low‑power design methodologies and power optimisation techniques.

Responsibilities

• Drive the physical implementation of ASIC/SoC designs.
• Work on synthesis, timing analysis, and optimisation to achieve best metrics.
• Collaborate with DFT engineers to integrate design‑for‑test structures.

Skills

Physical Design

Power Optimisation

Timing Analysis

Scripting Languages

Collaboration

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering or related field

Tools

Cadence Innovus

Synopsys ICC2

Mentor Graphics Calibre

Job description

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a highly skilled Senior/Principal Physical Design Engineer to contribute to our next‑generation chip designs. As a Physical Design Engineer, you will be responsible for the end‑to‑end implementation of complex IC physical designs, from synthesis to sign‑off. You will collaborate with cross‑functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities

• Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign‑off.
• Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
• Perform power planning and analysis, addressing IR drop, electromigration, and low‑power design techniques.
• Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
• Collaborate with DFT engineers to integrate design‑for‑test (DFT) structures into the physical implementation.
• Develop flows in EDA tools such as Cadence Innovus, Synopsys ICC2, Mentor Graphics Calibre, and others.
• Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
• Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical‑aware RTL design.

Preferred Qualifications

• Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
• 7+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
• Strong proficiency in EDA tools for place & route, STA, and sign‑off.
• Solid understanding of CMOS technology, semiconductor physics, and process limitations.
• Experience with low‑power design methodologies, power optimisation techniques, and multi‑power domain architectures.
• Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
• Proficiency in scripting languages like TCL, Perl, or Python for automation.
• Excellent problem‑solving skills, communication, and teamwork in a collaborative design environment.
• Experience in high‑performance computing (HPC), AI accelerators, or networking chips.