Lead DFT Engineer — AI Accelerator SoC, Equity

Fractile; West of England; Vor Ort; GBP 110.000 - 170.000; Vollzeit

Benefits dieser Stelle

Competitive salary

Equity ownership

Private medical

Dental and Vision

Contributory Pension

25 Days holiday + bank holidays

Life/Critical Illness Insurance

Diverse & inclusive culture

Zusammenfassung

Fractile in the United Kingdom is seeking a Lead/Principal DFT Engineer to own the DFT architecture for a high-performance AI accelerator SoC. You will define strategy, flow, and signoff criteria, and drive the integration of DFT tools within the EDA environment across multi-core designs and large memory systems.

You will work closely with RTL and physical design, bring up ATPG patterns on ATE, and mentor a team of DFT engineers to deliver robust, test-friendly silicon yield ramps.

Qualifikationen

• 10+ years experience in DFT for complex ASIC/SoC designs.
• Ownership of DFT architecture on at least one large tapeout.
• Deep expertise in scan, compression, ATPG and MBIST.
• Experience with industry tools (Synopsys or Tessent).
• Strong understanding of clocking, resets, power domains and physical constraints.
• Experience with silicon bring-up, debug and yield ramp.

Aufgaben

• Own and define the DFT architecture for a large AI accelerator SoC (scan, compression, MBIST, LBIST, boundary scan).
• Set DFT strategy, methodology, flow and signoff criteria.
• Drive integration of DFT tools and flows into the overall EDA environment.
• Define hierarchical DFT approach for multi-core designs and large memory systems.
• Define scan architecture, compression strategy, and ATPG approach.
• Define memory test and repair strategy for large embedded RAM.
• Establish power-aware and at-speed test strategies.
• Work closely with RTL and physical design to ensure clean DFT integration and timing closure.
• Work with test and product engineering teams to bring up and debug ATPG patterns on ATE, supporting production test and yield ramp.
• Mentor and guide DFT engineers

Kenntnisse

DFT for ASIC/SoC

DFT architecture ownership

Scan/Compression/ATPG/MBIST

Synopsys or Tessent

Clocking/Resets/Power domains

Silicon bring-up and debug

Tools

Synopsys/Tessent

Jobbeschreibung

Fractile in the United Kingdom is seeking a Lead/Principal DFT Engineer to own the DFT architecture for a high-performance AI accelerator SoC. You will define strategy, flow, and signoff criteria, and drive the integration of DFT tools within the EDA environment across multi-core designs and large memory systems.

You will work closely with RTL and physical design, bring up ATPG patterns on ATE, and mentor a team of DFT engineers to deliver robust, test-friendly silicon yield ramps.