Lead RTL Designer (PPA) – Equity & High-Impact Chip

Fractile; West of England; On-site; GBP 120,000 - 180,000; Full time

Benefits offered by this job

Equity & Ownership

Private Medical, Dental and Vision

Contributory Pension

25 Days holiday plus bank holidays

Life/Critical Illness Insurance

Job summary

Fractile in the United Kingdom is seeking a Lead RTL Designer with PPA experience to drive datapath RTL and end-to-end PPA closure for front-end hardware supporting AI inference at scale.

You will iteratively optimize fixed- and floating-point arithmetic, collaborate with synthesis and PD teams, and translate PPA targets into concrete RTL and microarchitectural decisions. This role includes equity and comprehensive benefits.

Qualifications

• Strong datapath microarchitecture background, including pipelining, retiming, and PPA vs area trade-offs.
• Track record of driving datapath PPA closure end-to-end: identifying bottlenecks, proposing RTL changes, and validating impact against targets.
• Good knowledge of fixed-point, floating-point, and/or quantized arithmetic design.
• Deep understanding of PPA trade-off analysis and translating targets into RTL/microarchitectural decisions.
• Experience with low-power design techniques.
• Experience writing timing-aware datapath RTL and iterating against synthesis/STA feedback to close timing on critical paths.
• Familiarity with synthesis tools (Synopsys Design Compiler, Fusion Compiler, Cadence Genus) and IP libraries (DesignWare).
• Demonstrated, measurable PPA improvements delivered on production datapath or compute silicon.
• Experience with formal verification or equivalence checking.
• Physical design awareness to collaborate with PD engineers on PPA closure

Responsibilities

• Develop datapath RTL and drive timing closure for high-performance compute silicon.
• Collaborate with synthesis, STA, and PD teams to optimize PPA and area.
• Translate PPA targets into concrete RTL and microarchitectural decisions.
• Support formal verification and equivalence checking efforts.
• Work with IP/generator libraries and ensure production-grade RTL quality.

Skills

Datapath RTL

PPA trade-offs

Low-power design

Formal verification

Timing analysis

Tools

Synopsys Design Compiler

Fusion Compiler

Cadence Genus

DesignWare

PrimeTime

Tempus

Job description

Fractile in the United Kingdom is seeking a Lead RTL Designer with PPA experience to drive datapath RTL and end-to-end PPA closure for front-end hardware supporting AI inference at scale.

You will iteratively optimize fixed- and floating-point arithmetic, collaborate with synthesis and PD teams, and translate PPA targets into concrete RTL and microarchitectural decisions. This role includes equity and comprehensive benefits.