Lead RTL Designer (PPA Experience)

Fractile; West of England; Sur place; GBP 120 000 - 180 000; Plein temps

Avantages offerts par ce poste

Equity & Ownership

Private Medical, Dental and Vision

Contributory Pension

25 Days holiday plus bank holidays

Life/Critical Illness Insurance

Résumé du poste

Fractile in the United Kingdom is seeking a Lead RTL Designer with PPA experience to drive datapath RTL and end-to-end PPA closure for front-end hardware supporting AI inference at scale.

You will iteratively optimize fixed- and floating-point arithmetic, collaborate with synthesis and PD teams, and translate PPA targets into concrete RTL and microarchitectural decisions. This role includes equity and comprehensive benefits.

Qualifications

• Strong datapath microarchitecture background, including pipelining, retiming, and PPA vs area trade-offs.
• Track record of driving datapath PPA closure end-to-end: identifying bottlenecks, proposing RTL changes, and validating impact against targets.
• Good knowledge of fixed-point, floating-point, and/or quantized arithmetic design.
• Deep understanding of PPA trade-off analysis and translating targets into RTL/microarchitectural decisions.
• Experience with low-power design techniques.
• Experience writing timing-aware datapath RTL and iterating against synthesis/STA feedback to close timing on critical paths.
• Familiarity with synthesis tools (Synopsys Design Compiler, Fusion Compiler, Cadence Genus) and IP libraries (DesignWare).
• Demonstrated, measurable PPA improvements delivered on production datapath or compute silicon.
• Experience with formal verification or equivalence checking.
• Physical design awareness to collaborate with PD engineers on PPA closure

Responsabilités

• Develop datapath RTL and drive timing closure for high-performance compute silicon.
• Collaborate with synthesis, STA, and PD teams to optimize PPA and area.
• Translate PPA targets into concrete RTL and microarchitectural decisions.
• Support formal verification and equivalence checking efforts.
• Work with IP/generator libraries and ensure production-grade RTL quality.

Connaissances

Datapath RTL

PPA trade-offs

Low-power design

Formal verification

Timing analysis

Outils

Synopsys Design Compiler

Fusion Compiler

Cadence Genus

DesignWare

PrimeTime

Tempus

Description du poste

About Fractile

Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.

The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.

Lead RTL Designer (PPA Experience)

About Fractile

Fractile was founded in 2022 on the bet that, eventually, the world’s most capable AI systems would be limited in their impact by the time taken to produce useful outputs. We bet everything on the logical conclusion: that the only way to truly unlock this latent value, to make speed viable at scale, was to radically re-invent the hardware that we run our frontier AI models on. Ever since, we have been building chips and systems that tackle this problem: how to efficiently generate output at thousands of tokens per second, while handling the complexity and capacity challenges of operating large models at very long contexts.

The workloads that push to the limits of the current frontier are already transformational; it is the technical and economic limits on inference speed that are constraining progress. The defining work of the 21st century will be marked by the engine of inference delivering immense and diffuse chains of intellectual inquiry, in drug discovery, in software engineering, in materials discovery, in any field where progress is driven by deep reasoning and intelligence to resolve complex problems.

Requirements:

• Strong datapath microarchitecture background: pipelining, retiming, and parallelism-vs-area trade-offs for PPA
• Track record of driving datapath PPA closure end-to-end: identifying bottlenecks, proposing RTL changes, and validating impact against targets
• Good knowledge of fixed-point, floating-point, and/or quantized arithmetic design
• Deep understanding of PPA trade-off analysis, and the ability to translate PPA targets into concrete RTL and microarchitectural decisions
• Experience with low-power design techniques
• Experience writing timing-aware datapath RTL and iterating against synthesis/STA feedback to close timing on critical paths
• Familiarity with synthesis tools (e.g. Synopsys Design Compiler/Fusion Compiler, Cadence Genus), and datapath IP/generator libraries (e.g. DesignWare)
• Demonstrated, measurable PPA improvements delivered on production datapath or compute silicon
• Experience with formal verification or equivalence checking
• Physical design awareness sufficient to collaborate effectively with PD engineers on PPA closure

Nice to Have:

• Experience with AI/ML accelerator datapath (e.g. systolic arrays, MAC/tensor engines) or other high-performance compute chip architectures
• Experience with static timing analysis tools (e.g. PrimeTime, Tempus)

What We Offer

• Competitive salary: A competitive salary reflective of your experience and the specialist nature of the role.
• Equity & Ownership: meaningful equity so everyone shares in the value creation
• Benefits: Private Medical, Dental and Vision, Contributory Pension, 25 Days holiday plus bank holidays and Life/Critical Illness Insurance.
• Diverse & fun office: we believe the hardest problems get solved by the broadest range of minds. We are committed to Equal Employment Opportunity through attracting and retaining a diverse team and building an inclusive environment.

Fractile is seeking to increase the clock speed of global progress, one chip at a time. We’ve recently raised $220M from investors including Founders Fund and Accel and our most important work lies ahead. Join us!

Export controls

Our work involves technologies subject to UK, US and other international export control regulations. Certain roles may require additional eligibility checks to ensure compliance with applicable law. We’ll be transparent about this throughout the hiring process.