Engineering Manager, Compilers — Lead AI Compiler Team (Hybrid UK)

Fractile; West of England; Hybride; GBP 120 000 - 190 000; Plein temps

Avantages offerts par ce poste

Equity

Private Medical

Pension

25 Days holiday

Life/Critical Illness Insurance

Résumé du poste

Fractile is building a full-stack AI accelerator. As Engineering Manager for Compilers, you will lead a 10+ engineer team delivering a compiler stack that enables industry-leading LLM inference on Fractile hardware, while collaborating with hardware, driver, runtime and ML teams.

You will shape architecture, IR design, and lowering strategies, taking ownership in a fast-paced environment to push performance from first principles to production silicon.

Qualifications

• Proven leadership experience managing a high-performance development team.
• Proven experience in compiler development, with ML compilers as an advantage.
• Up-to-date knowledge of machine learning techniques and technologies.
• Good understanding of computer architecture and performance optimization.
• Excellent C/C++ skills and experience with standard dev tools.
• Creative and innovative mindset with ownership and fast execution.

Responsabilités

• Build and lead a 10+ engineer compiler team for Fractile's AI accelerator.
• Define architecture of the compiler stack from first principles to early silicon.
• Collaborate with hardware, kernel, runtime and ML teams across the stack.
• Shape IR design, lowering strategy and execution model.
• Hire and grow a world-class team and drive performance of next-gen hardware.

Connaissances

Leadership experience

Compiler development

MLIR

TVM

ML techniques

Computer architecture

C/C++

Ownership & drive

Outils

MLIR

TVM

Description du poste

Fractile is building a full-stack AI accelerator. As Engineering Manager for Compilers, you will lead a 10+ engineer team delivering a compiler stack that enables industry-leading LLM inference on Fractile hardware, while collaborating with hardware, driver, runtime and ML teams.

You will shape architecture, IR design, and lowering strategies, taking ownership in a fast-paced environment to push performance from first principles to production silicon.