Lead RTL Design Engineer for Photonic Compute Path

TRIA; Leeds; Sur place; GBP 90 000 - 120 000; Plein temps

Avantages offerts par ce poste

Season ticket travel support

Résumé du poste

TRIA seeks a Senior RTL Design Engineer to lead RTL architecture and digital top-level integration for its photonic compute path. You will define the digital architecture, clock/reset strategy and interfaces, and write synthesizable RTL for control state machines and data paths.

Collaborate across photonics, analog, verification and layout teams through tapeout and first-silicon bring-up. 8+ years in ASIC RTL design with SystemVerilog, timing constraints and high-speed interfaces is required.

Qualifications

• 8+ years of ASIC RTL design and digital top integration.
• Strong SystemVerilog/Verilog knowledge with timing and synthesis focus.
• Experience with high-speed interfaces such as PCIe, CXL, UCIe and AXI/AMBA.
• Memory interfaces incl. DDR5/LPDDR/HBM and related protocols.
• CDC, reset design, low-power and hardware debug expertise.

Responsabilités

• Define the digital top architecture from scratch, including clock/reset strategy and register maps.
• Write synthesizable RTL for control state machines, data paths and PCS/MAC sub-layers.
• Lead RTL architecture and integration through tapeout with cross-functional teams.
• Collaborate with photonics, analogue, verification and layout engineers.

Connaissances

ASIC RTL design

SystemVerilog/Verilog

Synthesis & timing constraints

High-speed interfaces

Memory interfaces

CDC, reset design, low-power

Tapeout collaboration

Cadence flows

Python/Tcl scripting

Photonic exposure

Outils

Cadence flows

Python/Tcl scripting

Description du poste

TRIA seeks a Senior RTL Design Engineer to lead RTL architecture and digital top-level integration for its photonic compute path. You will define the digital architecture, clock/reset strategy and interfaces, and write synthesizable RTL for control state machines and data paths.

Collaborate across photonics, analog, verification and layout teams through tapeout and first-silicon bring-up. 8+ years in ASIC RTL design with SystemVerilog, timing constraints and high-speed interfaces is required.