Senior Design Engineer

TRIA; Leeds; On-site; GBP 90,000 - 120,000; Full time

Benefits offered by this job

Season ticket travel support

Job summary

TRIA seeks a Senior RTL Design Engineer to lead RTL architecture and digital top-level integration for its photonic compute path. You will define the digital architecture, clock/reset strategy and interfaces, and write synthesizable RTL for control state machines and data paths.

Collaborate across photonics, analog, verification and layout teams through tapeout and first-silicon bring-up. 8+ years in ASIC RTL design with SystemVerilog, timing constraints and high-speed interfaces is required.

Qualifications

• 8+ years of ASIC RTL design and digital top integration.
• Strong SystemVerilog/Verilog knowledge with timing and synthesis focus.
• Experience with high-speed interfaces such as PCIe, CXL, UCIe and AXI/AMBA.
• Memory interfaces incl. DDR5/LPDDR/HBM and related protocols.
• CDC, reset design, low-power and hardware debug expertise.

Responsibilities

• Define the digital top architecture from scratch, including clock/reset strategy and register maps.
• Write synthesizable RTL for control state machines, data paths and PCS/MAC sub-layers.
• Lead RTL architecture and integration through tapeout with cross-functional teams.
• Collaborate with photonics, analogue, verification and layout engineers.

Skills

ASIC RTL design

SystemVerilog/Verilog

Synthesis & timing constraints

High-speed interfaces

Memory interfaces

CDC, reset design, low-power

Tapeout collaboration

Cadence flows

Python/Tcl scripting

Photonic exposure

Tools

Cadence flows

Python/Tcl scripting

Job description

We're working with a pioneering UK deep-tech company building programmable silicon photonic compute, technology that performs operations directly within the data path instead of constantly moving data back and forth. Their work underpins breakthroughs in AI, cybersecurity and scientific research. They're a small, high-calibre team, so every hire makes a real difference.

They're looking for a Senior RTL Design Engineer to lead RTL architecture and digital top-level integration for the logic surrounding their photonic compute path. In short, you'd be the person making the digital side of a genuinely novel chip work.

What we're after

• 8+ years of ASIC RTL design and digital top integration
• Advanced SystemVerilog/Verilog, with a strong grasp of synthesis and timing constraints
• High-speed serial interfaces (PCIe, CXL, UCIe, AXI/AMBA) and memory interfaces (DDR5, LPDDR, HBM)
• Solid CDC, reset design, low-power and hardware debug experience
• A track record of taking designs through tapeout with mixed-signal and physical design teams
• Bonus points for 7/12nm, Cadence flows, Python/Tcl or any photonics exposure

What's in it for you?

• Season ticket travel support

This isn't a "maintain the block someone else built" role. You'll define the digital top architecture from the ground up, including clock and reset strategy, register maps and block-level interfaces. You'll also write synthesizable RTL for control state machines, data paths, side channels and custom PCS/MAC sub-layers.

You'll work hand in hand with photonics, analogue, verification and layout engineers, including the Director of Photonics. Your work will go right through tapeout and first-silicon bring-up in the lab. Few RTL roles in the UK put you this close to something this new.

If you want a role where your architecture decisions shape what a new class of compute can do, I'd love to hear from you.