Senior ASIC RTL Design & Verification Engineer

Synopsys, Inc.; Reading; On-site; GBP 80,000 - 110,000; Full time

Job summary

Synopsys, Inc. is seeking an experienced ASIC Digital Design Engineer to drive RTL design and verification for complex blocks and systems.

You will collaborate with Analog, physical design, and applications engineering to ensure integration and performance meet demanding specifications. You will develop comprehensive test plans, optimize performance and power with advanced EDA methodologies, and mentor junior engineers while staying current with industry trends to deliver high-quality, reliable

Qualifications

• Experience in ASIC digital design and RTL verification.
• Strong knowledge of DDR protocol implementations.
• Familiarity with industry-standard EDA tools and methodologies.

Responsibilities

• Lead design and verification of complex ASIC blocks and systems.
• Collaborate with Analog, physical design, and applications engineering teams.
• Develop and execute test plans to verify functionality and performance.
• Utilize EDA tools to optimize design performance and power efficiency.
• Mentor junior engineers and guide skill development.
• Stay updated with industry trends and technologies.

Skills

RTL design

ASIC digital design

Verification

DDR protocols

EDA tools

Communication

Job description

Synopsys, Inc. is seeking an experienced ASIC Digital Design Engineer to drive RTL design and verification for complex blocks and systems.

You will collaborate with Analog, physical design, and applications engineering to ensure integration and performance meet demanding specifications. You will develop comprehensive test plans, optimize performance and power with advanced EDA methodologies, and mentor junior engineers while staying current with industry trends to deliver high-quality, reliable