Senior Digital ASIC Design Engineer

Intellectual Capital Resources Ltd; West Yorkshire; On-site; GBP 70,000 - 110,000; Full time

Job summary

Intellectual Capital Resources Ltd is seeking a Senior Digital ASIC Design Engineer to contribute across the ASIC development flow from architecture and RTL to tapeout and silicon bring up.

You will collaborate with digital design, verification, analogue, physical design and system engineering teams to deliver robust, high-performance ASICs for a growing semiconductor company.

Qualifications

• Strong digital ASIC/RTL design experience.
• Advanced SystemVerilog or Verilog proficiency.
• Experience through the ASIC flow to tapeout.
• Digital top level integration experience.
• Good understanding of synthesis, timing and CDC.
• Experience working with cross functional engineering teams.

Responsibilities

• Developing synthesizable RTL for control logic, data paths, configuration and high performance digital blocks
• Defining and integrating digital architectures, including clocking, resets, registers and block level interfaces
• Working with high speed interfaces and protocols such as PCIe, CXL, UCIe, AXI or AMBA
• Integrating digital logic with memory, analogue and external interfaces
• Supporting RTL sign off through lint, CDC, RDC, synthesis, timing and formal analysis
• Working closely with verification and physical design teams to ensure designs are robust and ready for implementation
• Supporting FPGA prototyping, tapeout, silicon bring up and hardware debug
• Contributing to design reviews and helping solve complex technical challenges across the wider engineering team

Skills

Strong digital ASIC / RTL design

Advanced SystemVerilog or Verilog

ASIC flow to tapeout

Digital top level integration

Synthesis, timing and CDC

Cross-functional collaboration

Education

Degree in Electronics or Computer Engineering

Job description

A growing semiconductor company is expanding its digital design team and is looking for an experienced engineer to work on the development of complex ASIC technology. This is an opportunity to join a technically ambitious engineering team and contribute across the digital ASIC development flow, from architecture and RTL design through to tapeout and silicon bring up. As a Senior Digital ASIC Design Engineer, you will work across the design flow from architecture and RTL development through to tapeout and first silicon. You will collaborate closely with teams across digital design, verification, analogue, physical design and system engineering.

The role will involve:

• Developing synthesizable RTL for control logic, data paths, configuration and high performance digital blocks
• Defining and integrating digital architectures, including clocking, resets, registers and block level interfaces
• Working with high speed interfaces and protocols such as PCIe, CXL, UCIe, AXI or AMBA
• Integrating digital logic with memory, analogue and external interfaces
• Supporting RTL sign off through lint, CDC, RDC, synthesis, timing and formal analysis
• Working closely with verification and physical design teams to ensure designs are robust and ready for implementation
• Supporting FPGA prototyping, tapeout, silicon bring up and hardware debug
• Contributing to design reviews and helping solve complex technical challenges across the wider engineering team

Required experience:

• Strong digital ASIC / RTL design experience
• Advanced SystemVerilog or Verilog
• Experience through the ASIC flow to tapeout
• Digital top level integration experience
• Good understanding of synthesis, timing and CDC
• Experience working with cross functional engineering teams
• Degree in Electronics, Computer Engineering or a related subject