Senior Hardware Design Lead – RTL & FPGA/ASIC

AccelerComm Ltd; Bristol; Hybrid; GBP 90,000 - 130,000; Full time

Benefits offered by this job

We pay competitive salaries

Bonus up to 20% of salary annually

EMI share options

Pension

Job summary

AccelerComm is seeking a Principal Design Team Leader to guide RTL design and delivery of high-speed ASIC/FPGA IP for 5G base stations and space-qualified devices. You will shape technical roadmaps, drive architecture decisions, and deliver complex IP with a hands-on leadership style.

The role combines strategic planning with hands-on design oversight. You will mentor engineers, collaborate with Algorithm, Architecture and Software teams, and interact with customers during presales.

Qualifications

• Track record of building and leading high performing teams.
• Expert knowledge of RTL design (Verilog, SystemVerilog).
• Delivery of digital designs for ASIC and FPGA.
• Optimization of timing and hardware resources for high throughput/data processing.
• Expert user of EDA tools for simulation and synthesis.
• Knowledge of project management methodologies across the design lifecycle (agile/waterfall).
• Experience with UVM verification techniques.
• Experience with high-speed interfaces (AMBA/PCIe/JESD).
• C++/SystemC for design modelling and integration.

Responsibilities

• Provide strategic vision to inform technical decision-making and planning at a company level, working with Algorithm, System Architecture and Software teams.
• Take responsibility for the successful and timely delivery of projects by providing technical leadership
• Provide managerial leadership to build knowledge and support the team development
• Work closely with the exec team to translate product requirements into hardware team deliverables
• Support discussions with customers during presales and product development
• Oversee the implementation of designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches
• Lead AccelerComm's engineering methodology, processes, and design techniques, integrating AI where possible.
• Nurture professional growth of team members through regular mentoring, coaching, and feedback

Skills

RTL design

Verilog/SystemVerilog

ASIC/FPGA

Timing optimization

EDA tools

Team leadership

Project management

UVM

Hardware architecture

C++/SystemC modeling

Tools

UVM testbenches

Job description

AccelerComm is seeking a Principal Design Team Leader to guide RTL design and delivery of high-speed ASIC/FPGA IP for 5G base stations and space-qualified devices. You will shape technical roadmaps, drive architecture decisions, and deliver complex IP with a hands-on leadership style.

The role combines strategic planning with hands-on design oversight. You will mentor engineers, collaborate with Algorithm, Architecture and Software teams, and interact with customers during presales.