Senior RTL Architect for PCIe/CXL Interconnects

Arm Limited; United Kingdom; Hybrid; GBP 90,000 - 130,000; Full time

Job summary

Arm Limited is seeking an experienced RTL/SoC engineer to own microarchitecture and RTL development for high-speed interconnect subsystems, including PCIe, CXL, and UALink. You will translate requirements into microarchitecture specifications and synthesizable RTL, driving integration across multiple silicon products.

You will lead the development process from concept through RTL creation, subsystem integration, verification support, and final delivery, collaborating with architecture,

Qualifications

• 8+ years in RTL build, microarchitecture, or related semiconductor roles.
• Deep hands-on SystemVerilog expertise for high-performance digital subsystems.
• Experience with PCIe, CXL, UALink interconnects and memory systems.
• Understanding of AXI, CHI, ACE, and streaming interfaces.

Responsibilities

• Own microarchitecture, RTL development, and integration of high-speed interconnect subsystems.
• Lead RTL creation, subsystem integration, verification support, and delivery.
• Collaborate with architecture, verification, firmware, physical design, and implementation teams to meet targets.
• Mentor engineers and drive performance and reliability improvements.

Skills

SystemVerilog

RTL development

Microarchitecture

PCIe interconnects

CXL interconnects

UALink

Performance optimization

Team leadership

Education

Bachelor’s or Master’s degree in EE/CS or related field

Tools

Formal verification

Waveform debug

Job description

Arm Limited is seeking an experienced RTL/SoC engineer to own microarchitecture and RTL development for high-speed interconnect subsystems, including PCIe, CXL, and UALink. You will translate requirements into microarchitecture specifications and synthesizable RTL, driving integration across multiple silicon products.

You will lead the development process from concept through RTL creation, subsystem integration, verification support, and final delivery, collaborating with architecture,