Logic Design Engineer

TRIA; Leeds; In loco; GBP 90.000 - 130.000; Tempo pieno

Vantaggi offerti da questo lavoro

Generous time off

Descrizione del lavoro

TRIA in Leeds is seeking a Senior High-Speed Custom Logic Design Engineer to own timing-critical digital blocks at the heart of a fast‑path PHY that interconnects photonics, analogue and digital subsystems. You will shape microarchitecture, design SerDes datapaths, flip-flops and memory banks, and drive layout through tapeout and first-silicon bring-up.

You should have hands‑on experience with multi‑tapeout CMOS designs, strong timing and SI discipline, and Cadence Virtuoso/Spectre, with

Competenze

• Multiple tapeouts in CMOS digital or high-speed mixed-signal IC design.
• Strong transistor-level CMOS: datapaths, clocking, timing and SI trade-offs.
• Hands-on Cadence Virtuoso and Spectre (or similar).
• Taking logic from spec through layout sign-off to silicon debug.
• Advanced nodes (7nm/12nm, FinFET) a real plus.

Mansioni

• Own the timing-critical custom logic at the heart of a high-speed, compute-enabled PHY that links photonic, analogue and digital subsystems.
• Define the microarchitecture, design SerDes datapaths, flip-flops and memory banks, and guide layout through to tapeout and first-silicon bring-up.
• Work with the Director of Photonics and a small team of analogue, photonic and physical design engineers to balance trade-offs.

Conoscenze

Custom digital or high-speed mixed-sig

Transistor-level CMOS timing

Python, Tcl or SKILL automation

Logic to silicon flow

Strumenti

Cadence Virtuoso

Cadence Spectre

Descrizione del lavoro

Senior High-Speed Custom Logic Design Engineer

We're working with a pioneering UK deep-tech company building programmable silicon photonic compute, performing operations directly within the data path to support AI, cybersecurity and scientific workloads.

You will own the timing-critical custom logic at the heart of a high-speed, compute-enabled PHY that links photonic, analogue and digital subsystems.

What we're after:

• Custom digital or high-speed mixed-signal IC design, with multiple tapeouts
• Strong transistor-level CMOS: datapaths, clocking, timing and SI trade-offs
• Hands-on Cadence Virtuoso and Spectre (or similar)
• Taking logic from spec through layout sign-off to silicon debug
• Advanced nodes (7nm/12nm, FinFET) a real plus
• Python, Tcl or SKILL automation a bonus

What's in it for you?

Generous time off

This isn't block-level work on someone else's architecture. You'll define the microarchitecture, design SerDes datapaths, flip-flops and memory banks, and guide layout through to tapeout and first-silicon bring-up.

You'll work closely with the Director of Photonics and a small, sharp team of analogue, photonic and physical design engineers, making trade-offs that directly shape a genuinely new kind of compute.

If that sounds like your kind of challenge, get in touch for a confidential chat.