Senior High-Speed Custom Logic Engineer (Silicon Photonics)

TRIA; Leeds; On-site; GBP 90,000 - 130,000; Full time

Benefits offered by this job

Generous time off

Job summary

TRIA in Leeds is seeking a Senior High-Speed Custom Logic Design Engineer to own timing-critical digital blocks at the heart of a fast‑path PHY that interconnects photonics, analogue and digital subsystems. You will shape microarchitecture, design SerDes datapaths, flip-flops and memory banks, and drive layout through tapeout and first-silicon bring-up.

You should have hands‑on experience with multi‑tapeout CMOS designs, strong timing and SI discipline, and Cadence Virtuoso/Spectre, with

Qualifications

• Multiple tapeouts in CMOS digital or high-speed mixed-signal IC design.
• Strong transistor-level CMOS: datapaths, clocking, timing and SI trade-offs.
• Hands-on Cadence Virtuoso and Spectre (or similar).
• Taking logic from spec through layout sign-off to silicon debug.
• Advanced nodes (7nm/12nm, FinFET) a real plus.

Responsibilities

• Own the timing-critical custom logic at the heart of a high-speed, compute-enabled PHY that links photonic, analogue and digital subsystems.
• Define the microarchitecture, design SerDes datapaths, flip-flops and memory banks, and guide layout through to tapeout and first-silicon bring-up.
• Work with the Director of Photonics and a small team of analogue, photonic and physical design engineers to balance trade-offs.

Skills

Custom digital or high-speed mixed-sig

Transistor-level CMOS timing

Python, Tcl or SKILL automation

Logic to silicon flow

Tools

Cadence Virtuoso

Cadence Spectre

Job description

TRIA in Leeds is seeking a Senior High-Speed Custom Logic Design Engineer to own timing-critical digital blocks at the heart of a fast‑path PHY that interconnects photonics, analogue and digital subsystems. You will shape microarchitecture, design SerDes datapaths, flip-flops and memory banks, and drive layout through tapeout and first-silicon bring-up.

You should have hands‑on experience with multi‑tapeout CMOS designs, strong timing and SI discipline, and Cadence Virtuoso/Spectre, with