Design Team Leader

AccelerComm Ltd; West of England; Hybrid; GBP 110,000 - 140,000; Full time

Benefits offered by this job

EMI share options

Pension

Private health insurance

Hybrid working

Job summary

AccelerComm Ltd in Bristol, UK, is seeking a Design Team Leader to drive the hardware design roadmap for Layer 1 IP on 5G base stations and space-qualified devices.

You will lead a high-performance team, deliver complex RTL/IP for FPGA and ASIC, and partner with Algorithm, System Architecture and Software teams to translate product goals into tangible hardware solutions. Hybrid working and strong compensation offered.

Qualifications

• Proven track record of leading high-performing teams.
• Expert knowledge of RTL design (Verilog, SystemVerilog) for ASIC/FPGA products.
• Strong delivery of digital designs for ASIC and FPGA.
• Optimization of timing and hardware resources; power management, synthesis, timing analysis.
• Expert user of EDA tools for simulation and synthesis.
• Knowledge of design lifecycle methodologies across agile and waterfall.

Responsibilities

• Provide strategic vision to inform technical decision-making and planning at company level.
• Take responsibility for successful and timely project delivery via technical leadership.
• Provide managerial leadership to grow knowledge and team development.
• Work with exec team to translate product requirements into hardware deliverables.
• Support discussions with customers during presales and product development.
• Oversee FPGA/ASIC designs using industry standard techniques and UVM testbenches.

Skills

Track record of leading teams

RTL design Verilog/SystemVerilog

Digital design for ASIC/FPGA

Timing/resource optimization

EDA tools (simulation/synthesis)

Project management methodologies (Ag-<

Tools

UVM

C++/SystemC

Job description

Design Team Leader

Department: Hardware

Employment Type: Full Time

Location: Bristol, UK

Description

As the Principal Design Team Leader at AccelerComm, you will be working on 5G base stations on board satellites. This revolutionary technology is at the leading edge of non-terrestrial communications, and will underpin the next generation of mobile standards giving complete coverage to the globe. AccelerComm develop the baseband signal processing technology, using hardware acceleration to generate world-leading error resilience, capacity and power efficiency. The Principal Design Team Leader will take a leading role in shaping the technical roadmap for extending the power efficiency for the latest generation space-qualified devices, and then delivering this technology to our customers.

We are looking for a person with a proven track record of team leadership and delivering complex IP, who has a real interest in all aspects of the Intellectual Property development life cycle.

This is a hands-on role requiring exceptional team leadership skills alongside technical skills to drive the design, quality, and delivery of Layer 1 IP. This role will play a pivotal part in the growth of AccelerComm and our product portfolio

Key Responsibilities

• Provide strategic vision to inform technical decision-making and planning at a company level , working with colleagues from Algorithm, System Architecture and Software teams.
• Take responsibility for the successful and timely delivery of projects by providing technical leadership
• Provide managerial leadership to build knowledge and support the team development
• Work closely with the exec team to translate product requirements into hardware team deliverables
• Support discussions with customers during presales and product development
• Oversee the implementation of designs targeting both FPGA and ASIC using industry standard techniques, including the creation of UVM based testbenches
• Lead AccelerComm's engineering methodology, processes, and design techniques, integrating AI where possible.
• Nurture professional growth of team members through regular mentoring, coaching, and feedback

Skills, Knowledge and Expertise

Essential

• Track record of building and leading high performing collaborative teams
• Expert knowledge of RTL design (Verilog, SystemVerilog) for complex ASIC and FPGA products
• A strong skillset in delivery of digital designs for ASIC and FPGA
• Optimisation of timing and hardware resources for high throughput data or signal processing applications. Experience in power management techniques, synthesis and timing analysis
• Expert user of EDA tools for simulation and synthesis
• Knowledge and appreciation of project management methodologies across the design lifecycle including agile and waterfall, requirements capture and traceability.

Desirable

• Knowledge of communications signal processing algorithms (such as error correction, equalisation, channel estimation, beamforming)
• Understanding of UVM verification techniques or practical experience using UVM for IP verification
• Experience with high speed interfaces on and off chip such as AMBA, PCI-E or JESD
• Understanding of using C++/SystemC for design modelling and integration
• Experience in Technology Readiness Models
• Understanding of system architecture of a multi-disciplinary team project

Benefits

We pay competitive salaries which depend on skills and experience.

We offer a bonus scheme which pays up to 20% of salary annually, depending on performance. This is in addition to EMI share options, issued periodically. We offer a range of good quality company benefits including pension and private health insurance.

We operate flexible working hours and offer hybrid working.