Senior RTL Design Engineer - IoT Chipset Innovation

Sequans Communications Limited; Paris; Sur place; EUR 60 000 - 80 000; Plein temps

Résumé du poste

Sequans Communications Limited in Paris is looking for a VLSI team member to design and implement digital blocks for next-generation chipsets. Candidates should have at least 5 years of experience in ASIC/FPGA development and a strong command of hardware description languages.

The role involves optimization techniques, requirements analysis, and working closely with various teams. A degree in computer science or electrical engineering and fluent English are required.

Qualifications

• At least 5 years of experience in ASIC and/or FPGA development.
• Fast learning capabilities, highly motivated, self-starter.
• Excellent written and oral communications skills, fluent English.

Responsabilités

• Design (RTL coding) of key digital building blocks.
• Requirements analysis and micro architecture definition.
• Design optimization in the context of timing, power and area.

Connaissances

Hardware description languages (SystemVerilog/Verilog/VHDL)

Optimization techniques for high throughput, low area, low power

Multiple clock domain architectures

Front End activities (e.g. Lint, CDC, RDC tools)

Unix environment and shell programming/scripting

Version control systems (Git, SVN)

Formation

Degree (BSc/MSc/PhD) in computer science, electrical engineering or equivalent

Outils

Synthesis tools

Static timing analysis tools

Place and Route tools

Description du poste

Sequans Communications Limited in Paris is looking for a VLSI team member to design and implement digital blocks for next-generation chipsets. Candidates should have at least 5 years of experience in ASIC/FPGA development and a strong command of hardware description languages.

The role involves optimization techniques, requirements analysis, and working closely with various teams. A degree in computer science or electrical engineering and fluent English are required.