Senior Digital ASIC Design Engineer: Front-End & DfT Lead

microTECH Global Limited; Grenoble; Hybride; EUR 45 000 - 65 000; Plein temps

Résumé du poste

microTECH Global Limited in Grenoble, France, is seeking a Senior Digital Design Engineer to design digital blocks for ASICs across multiple markets. The role focuses on front-end digital design, synthesis, and DFT with emphasis on testability and verification in lab conditions.

You will work with VHDL/Verilog/SystemVerilog, script in Python/Tcl, and collaborate with customers and internal teams to specify architectures and drive design decisions from concept to silicon.

Qualifications

• Engineering degree (or equivalent) in microelectronics.
• 5+ years in Front-end ASIC digital design.
• Experience with VHDL/Verilog/SystemVerilog, and digital synthesis for DFT.
• Scripting in Python and Tcl.
• Fluent English. French speaking a plus.

Responsabilités

• Study, specify and design digital blocks and sub-systems with area and power estimations.
• Elaborate testability insertion strategy for circuit specifications.
• Perform verification up to test pattern generation for silicon measurements.
• Improve digital design flow, verification and test methods.
• Perform digital synthesis and DFT to reduce testing cost.
• Lead architecture discussions and present design status in reviews with customers.

Connaissances

VHDL

Verilog

SystemVerilog

Python

Tcl

Digital design

Formation

Engineering degree in microelectronics

Outils

Mentor

Synopsys

Cadence

Description du poste

microTECH Global Limited in Grenoble, France, is seeking a Senior Digital Design Engineer to design digital blocks for ASICs across multiple markets. The role focuses on front-end digital design, synthesis, and DFT with emphasis on testability and verification in lab conditions.

You will work with VHDL/Verilog/SystemVerilog, script in Python/Tcl, and collaborate with customers and internal teams to specify architectures and drive design decisions from concept to silicon.