Senior Digital Design Engineer

microTECH Global Limited; Grenoble; Hybride; EUR 45 000 - 65 000; Plein temps

Résumé du poste

microTECH Global Limited in Grenoble, France, is seeking a Senior Digital Design Engineer to design digital blocks for ASICs across multiple markets. The role focuses on front-end digital design, synthesis, and DFT with emphasis on testability and verification in lab conditions.

You will work with VHDL/Verilog/SystemVerilog, script in Python/Tcl, and collaborate with customers and internal teams to specify architectures and drive design decisions from concept to silicon.

Qualifications

• Engineering degree (or equivalent) in microelectronics.
• 5+ years in Front-end ASIC digital design.
• Experience with VHDL/Verilog/SystemVerilog, and digital synthesis for DFT.
• Scripting in Python and Tcl.
• Fluent English. French speaking a plus.

Responsabilités

• Study, specify and design digital blocks and sub-systems with area and power estimations.
• Elaborate testability insertion strategy for circuit specifications.
• Perform verification up to test pattern generation for silicon measurements.
• Improve digital design flow, verification and test methods.
• Perform digital synthesis and DFT to reduce testing cost.
• Lead architecture discussions and present design status in reviews with customers.

Connaissances

VHDL

Verilog

SystemVerilog

Python

Tcl

Digital design

Formation

Engineering degree in microelectronics

Outils

Mentor

Synopsys

Cadence

Description du poste

Job Title: Senior Digital Design Engineer

Location: Grenoble, France

Job Type: permanent

Salary: 45K – 65K dependant on experience

Client Overview

Designs analog and digital integrated circuits for internal teams and external customers.

Medical applications, consumer, automotive, industrial and other markets.

Role Responsibilities

• You study, specify and design digital blocks, sub-systems and/or top level, making area/power estimations
• You elaborate testability insertion strategy corresponding to the circuit specifications
• You perform verification tasks until the generation of test patterns for silicon measurements in our lab.
• You improve the digital design, functional and test mode verification flow
• You perform digital synthesis and Design for Test (DfT), using techniques that reduce the difficulty and cost associated when testing an integrated circuit
• You lead, debate and present the choice of architectures and design status during review meetings within the ASIC project team and in front of customers.

Experience Required

• Engineering degree (or equivalent) in microelectronics
• 5+ years in Front-end ASIC digital design
• Experience in VHDL and/or Verilog and/or SystemVerilog, and in digital synthesis for DFT
• Comfortable in scripting (python, tcl)
• Fluent English
• Bonuses:
  • French Speaking
  • knowledge of different tools (Mentor, Synopsys, Cadence)
  • Design in different languages (SystemVerilog, VHDL)
  • Experience in mixed ASIC environment.