Senior RTL Design Engineer – Paris

Sequans Communications Limited; Paris; Sur place; EUR 60 000 - 80 000; Plein temps

Résumé du poste

Sequans Communications Limited in Paris is looking for a VLSI team member to design and implement digital blocks for next-generation chipsets. Candidates should have at least 5 years of experience in ASIC/FPGA development and a strong command of hardware description languages.

The role involves optimization techniques, requirements analysis, and working closely with various teams. A degree in computer science or electrical engineering and fluent English are required.

Qualifications

• At least 5 years of experience in ASIC and/or FPGA development.
• Fast learning capabilities, highly motivated, self-starter.
• Excellent written and oral communications skills, fluent English.

Responsabilités

• Design (RTL coding) of key digital building blocks.
• Requirements analysis and micro architecture definition.
• Design optimization in the context of timing, power and area.

Connaissances

Hardware description languages (SystemVerilog/Verilog/VHDL)

Optimization techniques for high throughput, low area, low power

Multiple clock domain architectures

Front End activities (e.g. Lint, CDC, RDC tools)

Unix environment and shell programming/scripting

Version control systems (Git, SVN)

Formation

Degree (BSc/MSc/PhD) in computer science, electrical engineering or equivalent

Outils

Synthesis tools

Static timing analysis tools

Place and Route tools

Description du poste

At Sequans, we know that our success depends on our people, so we are always on the lookout for innovators, leaders, and visionaries. Our team is driven by a shared desire to lead in the IoT semiconductor and to push the limits of technology development.

Within the VLSI team, your responsibilities will be to specify, design, implement and verify various digital blocks linked to Sequans’ next chipsets generation. You will work closely with our software, signal processing algorithms, architecture, integration and verification teams and you will be responsible for planning, tracking and reporting activities related to the implementation of your digital blocks.

Responsibilities

• Design (RTL coding) of key digital building blocks.
• Requirements analysis and micro architecture (uarch) definition.
• Design optimization in the context of timing, power and area.
• Contribute to top-level integration, testing and debugging.
• Planning, Tracking and reporting of key activities.
• Preparing documentation and technical reports.
• Supporting verification and debugging.
• Third party IPs evaluation.

Experience and Skills

• Degree (BSc/MSc/PhD) in computer science, electrical engineering or equivalent studies.
• At least 5 years of working experience in ASIC and/or FPGA development.
• Strong command of hardware description languages (SystemVerilog/Verilog/VHDL).
• Background in optimization techniques for high throughput, low area, low power designs.
• Experience in multiple clock domains architectures.
• Experience in Front End activities (e.g Lint, CDC, RDC tools).
• Familiarity with Unix environment and shell programming/scripting (C-Shell, Tcl, Python).
• Experience in version control systems (Git, SVN).

Bonus Skills

• Knowledge of synthesis and static timing analysis tools.
• Knowledge of Place and Route.
• Experience in 3rd-Party IPs integration (NoC, RISC-V, memories, peripherals, etc).
• Exposure to LTE-M/NB-IoT, 4G LTE Cat 1bis, 5G NR.

Profile

• Fast learning capabilities, highly motivated, self-starter, autonomous
• Ability to work in a fast moving and multicultural environment
• Excellent written and oral communications skills, fluent English