Senior HW IP Designer — SoC Interconnect & RTL Architect

Qualcomm; Guyancourt; Sur place; EUR 100 000 - 140 000; Plein temps

Résumé du poste

Qualcomm France-QITC is seeking an experienced HW IP designer to shape the next generation of ASIC interconnects. You will drive unit specifications, collaborate with architecture and verification teams, and translate requirements into RTL code from product definitions.

You will function in a multi-site, international context, advancing debug and ECO processes and contributing to cutting-edge interconnect technology for Qualcomm’s SoC designs.

Qualifications

• Master’s degree in electrical engineering, digital design
• 8–10 years of microelectronics definition and design
• Ability to create robust micro-architectures.
• Ability to write clear specification documents.
• Proficient in RTL coding/simulation.
• Good knowledge of SOC/ASIC design flow.
• Knowledge of AMBA protocols, AXI, CHI, ...
• Self-driven with strong analytical and communication skills
• Ability to work in an international and multi-sites context.

Responsabilités

• Draft unit specifications from Product Definition Requirement documents.
• Review specifications with peers and verification team to start RTL coding and verification.
• Collaborate with the verification team to ensure specifications are understood and verified.
• Work with exploration and support teams as needed.
• Contribute expertise for debugging and ECO implementation when required.

Connaissances

Python

Verilog

C++

RTL coding

Git SVN

NcSim

French

English

Formation

Master’s degree in Electrical Engineering or digital design

Description du poste

Qualcomm France-QITC is seeking an experienced HW IP designer to shape the next generation of ASIC interconnects. You will drive unit specifications, collaborate with architecture and verification teams, and translate requirements into RTL code from product definitions.

You will function in a multi-site, international context, advancing debug and ECO processes and contributing to cutting-edge interconnect technology for Qualcomm’s SoC designs.