DFT Engineer – High-Speed Semiconductors (Lausanne/UK)

Kandou Ai; Saint-Sulpice; On-site; EUR 129,000 - 162,000; Full time

Job summary

Kandou Ai in Lausanne, Switzerland or UK is seeking a resourceful DFT Engineer to join our high-speed semiconductor team. You will work on hierarchical MBIST, scan insertion, ATPG patterns and IJTAG-based test development to improve chip test quality and yield.

You will collaborate with test and production teams, debug silicon issues, and define timing constraints for test modes. A strong background in DFT (5+ years), SystemVerilog knowledge and experience with EDA tools is required.

Qualifications

• 5+ years of DFT experience including implementation, test pattern development, and simulation
• Proven experience in contributing to DFT solution to complex designs
• Experience with IJTAG methodologies
• Experience with hierarchical MBIST insertion, hierarchical scan insertion and scan compression methodologies
• Experience in ATPG pattern generation for different kinds of fault models, fault coverage analysis and converging to high coverage metrics
• Good debug capabilities in simulating patterns with timing
• Experience with industry standard EDA tools for DFT, timing, and simulation
• Knowledge of System Verilog

Responsibilities

• Hierarchical MBIST and scan insertion, BSD implementation
• ATPG pattern generation, coverage analysis, converging to high coverage metrics
• Pattern simulations with timing
• Defining test mode timing constraints, analyzing the timing reports and converge timing
• Developing cycle accurate functional patterns using IJTAG methodology
• Closely working with the test and production engineering teams to debug and bring up devices at probe and final test
• Debugging silicon issues

Skills

Excellent communication skills

Excellent debugging skills

Good scripting skills to develop autom

Education

Bachelor of Engineering in Electronics and Electrical Engineering, Computer Engineering (equivalent or higher)

Tools

IJTAG

Job description

Kandou Ai in Lausanne, Switzerland or UK is seeking a resourceful DFT Engineer to join our high-speed semiconductor team. You will work on hierarchical MBIST, scan insertion, ATPG patterns and IJTAG-based test development to improve chip test quality and yield.

You will collaborate with test and production teams, debug silicon issues, and define timing constraints for test modes. A strong background in DFT (5+ years), SystemVerilog knowledge and experience with EDA tools is required.