Test Engineer

IC Resources; Nice; Vor Ort; EUR 40.000 - 55.000; Vollzeit

Zusammenfassung

A technology recruitment company is seeking a Junior DFT Engineer to join their R&D team in France. This role involves developing test strategies for ASIC and FPGA designs. Candidates should have a Master's in Electrical Engineering, along with 2-5 years of relevant experience. Strong debugging skills and familiarity with EDA tools are essential. Salary ranges from €40,000 to €55,000 based on experience.

Qualifikationen

• 2–5 years of hands-on DFT experience in ASIC and/or FPGA design.
• Familiarity with SoC test methodologies and industry standards.
• Strong debugging and problem-solving skills.

Aufgaben

• Contribute to the development and continuous improvement of DFT methodologies and flows.
• Implement and validate scan insertion, MBIST, LBIST, and other test structures.
• Collaborate with physical design and verification teams to identify and resolve DFT issues early.

Kenntnisse

DFT experience

Debugging skills

Scripting languages (TCL, Python)

Communication skills

Ausbildung

Master’s degree in Electrical Engineering or equivalent

Tools

EDA tools (Synopsys, Siemens, Cadence)

Jobbeschreibung

Business Manager - Semiconductor Division

Join a growing R&D team and contribute to the development of test strategies for next-generation ASIC and FPGA designs. This is an excellent opportunity for a Junior DFT Engineer with 2–5 years of experience to grow within a company with strong industry expertise and a collaborative culture.

As a Junior DFT Engineer, you will play a key role in the design, implementation, and validation of testability features in advanced digital systems, helping to ensure high-quality silicon bring-up and manufacturability.

Responsibilities

• Contribute to the development and continuous improvement of DFT methodologies and flows.
• Implement and validate scan insertion, MBIST, LBIST, and other test structures.
• Optimise test coverage, test time, and manufacturability.
• Collaborate with physical design and verification teams to identify and resolve DFT issues early in the flow.
• Develop automation scripts for test implementation, pattern generation, and analysis.
• Ensure compliance with industry standards and DFT best practices.

Required Qualifications

• Master’s degree in Electrical Engineering or equivalent.
• 2–5 years of hands-on DFT experience in ASIC and/or FPGA design.
• Knowledge of ATPG, JTAG, MBIST, LBIST, and related trade-offs between test quality and time.
• Proficiency in EDA tools (Synopsys, Siemens, or Cadence).
• Experience with scripting languages (TCL, Python, Perl) for automation.
• Strong debugging and problem-solving skills.
• Familiarity with SoC test methodologies and industry standards.
• Strong English communication skills (written and spoken).

Preferred Qualifications

• Experience with high-speed digital circuit design and testing.
• Familiarity with advanced packaging technologies (Multi-Die 2.5D/3D) and FPGA architectures.
• Knowledge of silicon bring-up and debug processes.
• Understanding of RTL (VHDL, Verilog, SystemVerilog) and low-power design methodologies.

Additional Information

• Must be eligible to work in France.
• Salary €40,000-€55,000 depending on experience

Seniorities

• Mid-Senior level

Employment type

• Full-time

Job function

• Industries: Computer Hardware Manufacturing and Semiconductor Manufacturing