Junior DFT Engineer - ASIC/FPGA Test & Validation

IC Resources; Nice; On-site; EUR 40,000 - 55,000; Full time

Job summary

A technology recruitment company is seeking a Junior DFT Engineer to join their R&D team in France. This role involves developing test strategies for ASIC and FPGA designs. Candidates should have a Master's in Electrical Engineering, along with 2-5 years of relevant experience. Strong debugging skills and familiarity with EDA tools are essential. Salary ranges from €40,000 to €55,000 based on experience.

Qualifications

• 2–5 years of hands-on DFT experience in ASIC and/or FPGA design.
• Familiarity with SoC test methodologies and industry standards.
• Strong debugging and problem-solving skills.

Responsibilities

• Contribute to the development and continuous improvement of DFT methodologies and flows.
• Implement and validate scan insertion, MBIST, LBIST, and other test structures.
• Collaborate with physical design and verification teams to identify and resolve DFT issues early.

Skills

DFT experience

Debugging skills

Scripting languages (TCL, Python)

Communication skills

Education

Master’s degree in Electrical Engineering or equivalent

Tools

EDA tools (Synopsys, Siemens, Cadence)

Job description

A technology recruitment company is seeking a Junior DFT Engineer to join their R&D team in France. This role involves developing test strategies for ASIC and FPGA designs. Candidates should have a Master's in Electrical Engineering, along with 2-5 years of relevant experience. Strong debugging skills and familiarity with EDA tools are essential. Salary ranges from €40,000 to €55,000 based on experience.