Design Engineer

Intellectual Capital Resources Ltd; Aix-en-Provence; Hybride; EUR 90 000 - 125 000; Plein temps

Avantages offerts par ce poste

Hybrid working

Competitive salary

Employee Stock Purchase Plan

Health insurance

Pension benefits

Team meals

Résumé du poste

Intellectual Capital Resources Ltd. is seeking a Senior Digital Design Engineer in Aix-en-Provence to work on next-generation PCIe, CXL and AMBA IP. The role involves architecture, microarchitecture and RTL implementation for high-performance connectivity solutions used in data centres.

You will join an international engineering team, contributing from architecture through FPGA prototyping while enjoying a hybrid model with onsite and remote days.

Qualifications

• 5+ years RTL design experience.
• Strong Verilog/SystemVerilog skills.
• Experience with digital IP design and microarchitecture.
• Master's or PhD in Electrical/Computer Engineering or related field.
• Good English communication skills.
• PCIe or CXL experience is desirable.

Responsabilités

• Contribute to architecture and microarchitecture of PCIe/CXL/AMBA IP.
• Develop and implement RTL using Verilog and SystemVerilog.
• Collaborate with verification engineers throughout development lifecycle.
• Support FPGA prototyping and validation of new IP designs.
• Work with international design teams on advanced semiconductor technologies.

Connaissances

RTL design

Verilog

SystemVerilog

Digital IP design

Microarchitecture

PCIe/CXL

English

Formation

Master's or PhD in Electrical/Computer Engineering

Description du poste

Senior Digital Design Engineer - PCIe / CXL / RTL

Location: Aix en Provence, France

Working Model: Hybrid, 3 days onsite / 2 days remote

Employment: Permanent, Full-Time

An established global semiconductor company is looking for a Senior Digital Design Engineer to join its growing Silicon IP team in Aix-en-Provence.

This is an opportunity to work on next-generation PCIe, CXL and AMBA controller IP, contributing to the architecture, microarchitecture and RTL implementation of high-performance connectivity solutions used in advanced computing and data centre applications.

You'll join an experienced international engineering team, working on technically challenging IP development projects with opportunities to contribute from initial architecture through to FPGA prototyping.

Responsibilities

• Contribute to the architecture and microarchitecture of next-generation PCIe, CXL and AMBA controller IP.
• Develop and implement RTL using Verilog and SystemVerilog.
• Collaborate closely with verification engineers throughout the development lifecycle.
• Support FPGA prototyping and validation of new IP designs.
• Work alongside international design teams on advanced semiconductor technologies.

Requirements

• 5+ years of professional RTL design experience.
• Strong Verilog / SystemVerilog skills.
• Experience with digital IP design and microarchitecture.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or a related discipline.
• Good English communication skills.
• Experience with PCIe or CXL is highly desirable but not essential. Strong RTL designers with relevant IP development experience are encouraged to apply.

What's on Offer?

• Competitive salary plus performance bonus.
• Employee Stock Purchase Plan.
• Hybrid working with two days remote per week.
• Comprehensive family health insurance.
• Additional annual leave.
• Pension and savings benefits.
• Regular team lunches, breakfasts and a collaborative engineering environment.
• The opportunity to work on industry-leading connectivity IP within an established semiconductor business.