ASIC Design Engineer

IC Resources; Île-de-France; Sur place; EUR 65 000 - 75 000; Plein temps

Résumé du poste

IC Resources in France is seeking a Staff Hardware Design Engineer to work on interconnect technology at the heart of NoC/IP and SoC architectures. You will define architecture specs and design RTL blocks for configurable networks.

You will collaborate across hardware, software and application engineering, contributing to verification, synthesis, timing, power and DFT, and pushing NoC functionality from concept to silicon.

Qualifications

• 5+ years of ASIC / SoC / IP design experience.
• Strong knowledge of RTL design, SystemVerilog, Verilog and VHDL.
• Experience with synthesis, STA, timing and power closure.
• Familiarity with NoC and AMBA/AXI/PCIe protocols.

Responsabilités

• Define architecture specifications for complex NoC / SoC IP.
• Design and develop RTL hardware blocks.
• Work across the full ASIC design flow including verification, timing and power.
• Contribute to verification, synthesis, timing, power and DFT.

Connaissances

RTL Design

SystemVerilog

Verilog

VHDL

SoC Design

NoC

ASIC Design

Synthesis

STA

DFT

Timing Closure

Power Closure

Outils

AMBA

AXI

PCIe

CXL

OCP

ARM

RISC-V

SystemC

C++

Python

Cadence

Synopsys

Siemens EDA

Description du poste

Want to work on the interconnect technology sitting at the heart of some of the world's most advanced SoCs? I'm working with a global semiconductor IP company whose technology is used across AI, automotive, consumer electronics, data centres, satellites and advanced computing. They are now hiring a Staff Hardware Design Engineer to work on highly configurable Network-on-Chip (NoC) IP and complex SoC architectures.

What you'll work on

• Define architecture specifications for complex NoC / SoC IP
• Design and develop RTL hardware blocks
• Work across the full ASIC design flow
• Contribute to verification, synthesis, timing, power and DFT
• Work closely with hardware, software and application engineering teams
• Support existing IP and help solve complex technical issues
• Influence the evolution of highly configurable interconnect products

What they're looking for

You’ll ideally have 5+ years of ASIC / SoC / IP design experience, with strong knowledge of:

• RTL Design
• SystemVerilog
• Verilog
• VHDL
• SoC Design
• NoC
• ASIC Design
• Synthesis
• STA
• DFT
• Timing Closure
• Power Closure

Experience with some of the following would be particularly relevant:

• AMBA
• AXI
• PCIe
• CXL
• OCP
• ARM
• RISC-V
• SystemC
• C++
• Python
• Cadence
• Synopsys
• Siemens EDA

Why consider it?

This is a strong opportunity for an experienced RTL / SoC designer who wants to move beyond isolated block design and work closer to system-level architecture and advanced interconnect IP. You'll be working on technology designed to solve one of the biggest challenges in modern semiconductor development: efficiently connecting increasingly complex processors, accelerators, memory and IP inside large SoCs.

Salary: €65,000-€75,000 gross baseLocation: Montigny-le-Bretonneux, FranceEligibility: Candidates should already have the right to work in France / the EU