PCIe ASIC Design Engineer

IC Resources; Provence-Alpes-Côte d'Azur; Hybrid; EUR 90,000 - 120,000; Full time

Benefits offered by this job

Employee Stock Purchase Plan

Hybrid working with two days remote

Pension and savings benefits

Regular team lunches

Job summary

IC Resources in Aix-en-Provence is seeking an experienced Senior Digital Design Engineer to join its Silicon IP team. You will contribute to architecture, microarchitecture and RTL implementation of high-performance PCIe, CXL and AMBA controller IP for data centre applications, collaborating with an international engineering group.

The role involves RTL development in Verilog/SystemVerilog, architectural trades, FPGA prototyping and close cooperation with verification teams, with two remote days

Qualifications

• 5+ years of professional RTL design experience.
• Experience with digital IP design and microarchitecture.
• Master's degree or PhD in Electrical Engineering or a related discipline.

Responsibilities

• Contribute to the architecture and microarchitecture of next-generation PCIe, CXL and AMBA controller IP.
• Develop and implement RTL using Verilog and SystemVerilog.
• Collaborate closely with verification engineers throughout the development lifecycle.
• Support FPGA prototyping and validation of new IP designs.
• Work alongside international design teams on advanced semiconductor technologies.

Skills

RTL design

Digital IP development

PCIe/CXL IP experience

Collaboration

Education

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Verilog/SystemVerilog

Job description

Working Model: Hybrid, 3 days onsite / 2 days remote

Employment: Permanent, Full-Time

An established global semiconductor company is looking for a Senior Digital Design Engineer to join its growing Silicon IP team in Aix-en-Provence.

This is an opportunity to work on next-generation PCIe, CXL and AMBA controller IP, contributing to the architecture, microarchitecture and RTL implementation of high-performance connectivity solutions used in advanced computing and data centre applications.

You'll join an experienced international engineering team, working on technically challenging IP development projects with opportunities to contribute from initial architecture through to FPGA prototyping.

Responsibilities

• Contribute to the architecture and microarchitecture of next-generation PCIe, CXL and AMBA controller IP.
• Develop and implement RTL using Verilog and SystemVerilog.
• Collaborate closely with verification engineers throughout the development lifecycle.
• Support FPGA prototyping and validation of new IP designs.
• Work alongside international design teams on advanced semiconductor technologies.

Requirements

• 5+ years of professional RTL design experience.
• Experience with digital IP design and microarchitecture.
• Master's degree or PhD in Electrical Engineering, Computer Engineering or a related discipline.
• Experience with PCIe or CXL is highly desirable but not essential. Strong RTL designers with relevant IP development experience are encouraged to apply.

What's on Offer?

• Competitive salary plus performance bonus.
• Employee Stock Purchase Plan.
• Hybrid working with two days remote per week.
• Additional annual leave.
• Pension and savings benefits.
• Regular team lunches, breakfasts and a collaborative engineering environment.
• The opportunity to work on industry-leading connectivity IP within an established semiconductor business.