Digital Design Engineer

Intellectual Capital Resources Ltd; Provence-Alpes-Côte d'Azur; Hybrid; EUR 60,000 - 90,000; Full time

Job summary

Intellectual Capital Resources Ltd in Sophia Antipolis, France, seeks a Digital Design Engineer to join a Bluetooth IP group. Hybrid work with around three days onsite per week, in a dynamic semiconductor environment.

You will work from microarchitecture through RTL, verification and FPGA prototyping, taking ownership of your designs to fit into the wider wireless system. This role offers exposure to real commercial technology and full digital design flow experiences.

Qualifications

• 3+ years hands-on Digital Design / RTL experience.
• Strong Verilog or SystemVerilog.
• Experience with ASIC, SoC or FPGA development.
• Solid understanding of the digital design flow, including microarchitecture, RTL, testbenches, verification, synthesis and code coverage.
• Experience implementing designs on FPGA.
• Ability to take ownership of your work and operate with autonomy.
• A degree in Electronics, Electrical Engineering, Computer Engineering, Embedded Systems or a related field.
• Experience with Bluetooth, Wi‑Fi, UWB, 802.15.4, Cellular / 3GPP or other wireless standards would be a strong advantage.

Responsibilities

• Design and develop Bluetooth / 802.15.4 MAC and PHY modules; contribute to microarchitecture.
• RTL design using Verilog / SystemVerilog and verification.
• Develop testbenches and coverage; perform synthesis and co-simulation.
• Prototype designs on FPGA for prototyping and validation.
• Collaborate with architecture, systems, algorithms, software, hardware and validation teams.

Skills

Digital design RTL

Verilog SystemVerilog

ASIC SoC FPGA

Digital design flow

Autonomy ownership

Education

Electronics / related degree

Job description

Digital Design Engineer – RTL / ASIC / Bluetooth

Sophia Antipolis, France | Hybrid

I’m working with an established semiconductor IP company in Sophia Antipolis that is expanding its hardware team and looking for a Digital Design Engineer to join a specialist Bluetooth IP group.

This is a hands‑on role for someone who wants to do more than simply code RTL.

You’ll be involved from microarchitecture through RTL design, verification and FPGA prototyping, taking ownership of your work and seeing how your designs fit into the wider wireless system.

The team develops advanced connectivity IP used at significant scale, giving you the chance to work on real commercial technology while building deeper experience across the full digital design flow.

What you’ll be working on

You’ll contribute to the design and development of advanced Bluetooth / 802.15.4 MAC and PHY modules, including:

• Defining microarchitecture
• RTL design using Verilog / SystemVerilog
• Taking ownership of design and verification
• Developing testbenches and supporting code coverage
• Synthesis and co-simulation
• Implementing designs on FPGA for prototyping
• Supporting validation and product certification
• Working closely with architecture, systems, algorithms, software, hardware and validation teams
• Producing documentation covering microarchitecture, interfaces and module-level testing
• Contributing ideas around tools, methodology and engineering processes

What they’re looking for

You’ll ideally have:

• 3+ years of hands‑on Digital Design / RTL experience
• Strong Verilog or SystemVerilog
• Experience with ASIC, SoC or FPGA development
• A solid understanding of the digital design flow, including microarchitecture, RTL, testbenches, verification, synthesis and code coverage
• Experience implementing designs on FPGA
• The ability to take ownership of your work and operate with a good level of autonomy
• A degree in Electronics, Electrical Engineering, Computer Engineering, Embedded Systems or a related field
• Experience with Bluetooth, Wi-Fi, UWB, 802.15.4, Cellular / 3GPP or other wireless communication standards would be a strong advantage.
• Knowledge of SoC architecture, subsystem architecture or IP integration would also be useful.

Why consider it?

This role gives you exposure to considerably more than just RTL implementation.

You’ll have the opportunity to work on microarchitecture, design, verification and FPGA prototyping, while learning from engineers with deep experience in wireless connectivity and semiconductor IP.

It’s a strong environment for someone who wants to develop broader technical ownership and move towards more complex subsystem and architecture work over time.

You’ll also be joining a smaller engineering environment where your work is visible and where you can work closely with teams across the wider product rather than being confined to one narrow area.

Location

Sophia Antipolis, France

Hybrid working, with around 3 days per week onsite.

Candidates will need existing eligibility to work in France, as new visa sponsorship cannot currently be supported.