Lead ASIC Verification Engineer – Exascale HPC

Atos; Madrid; Sur place; EUR 90 000 - 120 000; Plein temps

Avantages offerts par ce poste

Learning and Growth opportunities

Résumé du poste

Bull is seeking an experienced Asic Verification Lead to join our team in Madrid or Barcelona. You will drive verification strategy for high-end ASIC architectures, lead UVM-based verification efforts, and collaborate with architecture and design teams to ensure reliability and performance of advanced semiconductors.

The role emphasizes mentoring junior engineers, developing coverage models, and defining verification environments to achieve timely and robust validation for exascale servers.

Qualifications

• 8+ years of experience in ASIC verification.
• Experience leading ASIC functional verification teams.
• Proven track in verifying complex SoCs/ASICs.
• Experience with UVM or equivalent verification frameworks.

Responsabilités

• Acquire knowledge of architecture and microarchitecture by studying specifications and interacting with architecture/design teams.
• Define verification strategies and environments; develop, maintain and publish verification specs.
• Write and execute test plans with the logical design team.
• Develop coverage models and verification environments using UVM-SystemVerilog / C++.
• Monitor, analyze and debug simulation errors.
• Analyze simulation coverage to improve tests and hit coverage targets on time.
• Suggest tools and methodologies to improve productivity.
• Mentor junior engineers to produce maintainable and reusable code across projects.

Connaissances

ASIC verification leadership

SoC/ASIC verification

Constrained-Random UVM

UVM methodology

Team mentoring

Formation

Bachelor's Degree (BE / BTech) or Master's Degree (ME / MTech)

Outils

UVM-SystemVerilog

C++

Description du poste

Bull is seeking an experienced Asic Verification Lead to join our team in Madrid or Barcelona. You will drive verification strategy for high-end ASIC architectures, lead UVM-based verification efforts, and collaborate with architecture and design teams to ensure reliability and performance of advanced semiconductors.

The role emphasizes mentoring junior engineers, developing coverage models, and defining verification environments to achieve timely and robust validation for exascale servers.