Lead High-Speed Verification Engineer – PCIe/UCIe

Hireroo Ltd; Barcelona; Híbrido; EUR 90.000 - 140.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Flexible working hours

Hybrid model: 4 days in office, 1 day?

Relocation bonus

Housing search support

Visa support

Language classes

Private medical insurance

Virtual shares

Monthly food allowance

Descripción de la vacante

Hireroo Ltd is seeking a Lead Design Verification Engineer in Barcelona to lead functional verification of high-speed interface protocol blocks at IP and subsystem levels. The role blends hands-on verification with technical leadership across RTL, architecture, firmware and verification teams.

You will architect and maintain UVM environments, own verification of PCIe/UCIe/SerDes, and act as protocol expert for AXI, CXS, AHB, CHI.

Formación

• 10+ years of ASIC or SoC verification experience.
• Recent high speed protocol verification experience.
• Strong PCIe, UCIe or SerDes knowledge.
• Deep AXI, CXS, AHB or CHI expertise.
• Strong SystemVerilog and UVM.
• Coverage driven verification and sign off.
• Strong SoC and digital design knowledge.
• VCS, Xcelium or Questa familiarity.
• Excellent debugging and problem solving skills.
• Bachelor or Master degree in Electrical Engineering, Computer Engineering or related field.

Responsabilidades

• Lead IP and subsystem level functional verification.
• Architect and maintain UVM verification environments.
• Own verification of PCIe, UCIe, SerDes and related interfaces.
• Act as protocol expert for AXI, CXS, AHB and CHI.
• Debug RTL, DV model and specification mismatches.
• Drive coverage closure and sign off.
• Triage simulation failures and drive bug resolution.
• Develop scripts and verification automation.
• Guide and support verification engineers.
• Maintain verification methodology and technical documentation.

Conocimientos

ASIC/SoC verification

High speed protocol

PCIe/UCIe/SerDes

AXI/CXS/AHB/CHI

SystemVerilog/UVM

Coverage driven verification

SoC/digital design

Debugging

Bachelor/Master degree (EE/CE)

Educación

Bachelor or Master degree in Electrical Engineering, Computer Engineering or related field

Herramientas

VCS

Xcelium

Questa

Descripción del empleo

Hireroo Ltd is seeking a Lead Design Verification Engineer in Barcelona to lead functional verification of high-speed interface protocol blocks at IP and subsystem levels. The role blends hands-on verification with technical leadership across RTL, architecture, firmware and verification teams.

You will architect and maintain UVM environments, own verification of PCIe/UCIe/SerDes, and act as protocol expert for AXI, CXS, AHB, CHI.