Flight-Ready FPGA Verification Engineer

Aistech Space; Barcelona; Híbrido; EUR 70.000 - 100.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

On-site gym

Paddle tennis courts

Fresh fruit and coffee

Hybrid work

23 vacation days

Descripción de la vacante

Aistech Space in Barcelona seeks an expert FPGA Verification & Validation Engineer to define and execute the verification strategy for next-gen image payloads. You’ll ensure 100% reliability, timing compliance, and flawless performance before flight. Work in agile teams, building scalable testbenches and HIL frameworks.

Key objectives include advanced verification frameworks, Xilinx VIP usage, and robust AI engine/memory validation. Hybrid work with strong documentation culture is offered.

Formación

• Proven experience in advanced FPGA verification methodologies (UVVM, OSVVM, or UVM).
• Strong AMD/Xilinx toolchain proficiency (Vivado, Vitis, and simulators).
• Fluency in Python for automation and Tcl for workflow scripting.
• Solid knowledge of AXI4 protocol family and verification patterns.
• Excellent English communication for global collaboration.

Responsabilidades

• Architect and implement self-checking testbenches and verification environments.
• Lead hardware-in-the-loop (HIL) and flight-model verification campaigns.
• Verify high-speed I/O (GTH/GTY), MIPI CSI-2, PCIe Gen3/4, 10G/25G Ethernet.
• Validate data paths with AXI4-Stream and related IPs (VDMA, DataMover).
• Develop automation scripts in Tcl/Python for testing and results analysis.
• Document validation plans, test reports, and manuals.

Conocimientos

UVVM/OSVVM/UVM

Python scripting

Tcl scripting

AXI4 protocol

Xilinx Vivado/Vitis

VHDL verification

Agile teamwork

English communication

Educación

BSc/MSc Electronics

BSc/MSc Telecommunications

BSc/MSc Computer Science

Herramientas

Vivado

Vitis

ModelSim

QuestaSim

XSIM

Xilinx VIP

Descripción del empleo

Aistech Space in Barcelona seeks an expert FPGA Verification & Validation Engineer to define and execute the verification strategy for next-gen image payloads. You’ll ensure 100% reliability, timing compliance, and flawless performance before flight. Work in agile teams, building scalable testbenches and HIL frameworks.

Key objectives include advanced verification frameworks, Xilinx VIP usage, and robust AI engine/memory validation. Hybrid work with strong documentation culture is offered.